CY22801_12 Datasheet, PDF (6/25 Pages) Cypress Semiconductor – Universal Programmable Clock Generator (UPCG)

CY22801
DIV1N[0CH]
DIV1SRC[0CH]
REF
Qtotal
(Q+2)
[42H]
DIV2SRC[47H]
DIV1N[47H]
CLKOE[09H]
Figure 4. Basic Block Diagram of CY22801 PLL
PFD
VCO
Ptotal
(2(PB+4)+PO)
[40H, 41H, 42H]
CLKSRC
Crosspoint
Divider Bank 1 Switch Matrix
/DIV1N
/2
[45H]
/3
Divider Bank 2
/DIV2N
[44H, 45H]
/4
[45H, 46H]
/2
CLKA
CLKB
CLKC
Default Startup Condition for the CY22801
The default (programmed) condition of the device is generally set
by the distributor who programs the device using a customer
specific JEDEC file produced by CyClocksRT. Parts shipped
from the factory are blank and unprogrammed. In this condition,
all bits are set to 0, all outputs are three-stated, and the crystal
oscillator circuit is active.
While you can develop your own subroutine to program any or
all of the individual registers described in the following pages, it
may be easier to use CyClocksRT to produce the required
register setting file ^[6].
The serial interface address of the CY22801 is 69H. If there is a
conflict with any other devices in your system, then this can also
be changed ^[7][8].
Frequency Calculations and Register
Definitions using the Serial (I²C) Interface
The CY22801 provides an industry standard serial interface for
volatile, in-system programming of unique frequencies and
options. Serial programming and reprogramming allows for quick
design changes and product enhancements, eliminates
inventory of old design parts, and simplifies manufacturing.
The I²C Interface provides volatile programming. This means
when the target system is powered down, the CY22801 reverts
to its pre-I²C state, as defined above (programmed or
unprogrammed). When the system is powered back up again,
the I²C registers must be reconfigured again.
All programmable registers in the CY22801 are addressed with
eight bits and contain eight bits of data. The CY22801 is a slave
device with an address of 1101001 (69H).
Table 3 lists the I²C registers and their definitions. Specific
register definitions and their allowable values are listed as
follows.
Reference Frequency
The REF can be a crystal or a driven frequency (CLKIN). For
crystals, the frequency range must be between 8 MHz and
30 MHz. For a driven frequency, the frequency range must be
between 1 MHz and 133 MHz.
Programmable Crystal Input Oscillator Gain Settings
The Input crystal oscillator gain (XDRV) is controlled by two bits
in register 12H and are set according to Table 4 on page 8. The
parameters controlling the gain are the crystal frequency, the
internal crystal parasitic resistance (ESR, available from the
manufacturer), and the CapLoad setting during crystal startup.
Bits 3 and 4 of register 12H control the input crystal oscillator gain
setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The
setting is programmed according to Table 4 on page 8. All other
bits in the register are reserved and should be programmed as
shown in Table 5 on page 8.
FTAAddrSrc[1:0] bits set Frequency tuning array address
source. This will be set by CyClockRT software based on
selected configuration.
Notes
6. Advanced features like VCXO, SCL, SDA, FS, OE, SSON are not supported by CyClocksRT. Contact your local Cypress field application engineer for functional
feasibility and custom configuration with these advanced features.
7. Please Contact your local Cypress FAE, if you need serial interface address other than 69H.
8. while configuring Jedec through CyClocksRT software, if Pin3 (SDAT) and Pin5 (SCLK) is not configured for any functionality, the jedec file automatically gets configured
with I2C Enable Functionality with default I2C address as 69 H.
Document Number: 001-15571 Rev. *H
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