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CY22801_12 Datasheet, PDF (1/25 Pages) Cypress Semiconductor – Universal Programmable Clock Generator (UPCG)
CY22801
Universal Programmable Clock Generator
(UPCG)
Universal Programmable Clock Generator (UPCG)
Features
■ Integrated phase-locked loop (PLL)
■ Field-Programmable
■ Input frequency range:
❐ Crystal: 8 MHz to 30 MHz
❐ CLKIN: 1 MHz to 133 MHz
■ Low-voltage complementary metal oxide
(LVCMOS) output frequency:
❐ 1 MHz to 200 MHz (commercial grade)
❐ 1 MHz to 166.6 MHz (industrial grade)
semiconductor
■ Special Features:
❐ Spread Spectrum
❐ VCXO
❐ Inputs: PD or OE, FS
■ Low-jitter, high-accuracy outputs
■ 3.3 V operation
■ Commercial and industrial temperature ranges
■ 8-pin small-outline integrated circuit (SOIC) package
■ Serial interface for device configuration
General Description
The CY22801 is a flash-programmable clock generator that
supports various applications in consumer and communications
markets. The device uses the Cypress-proprietary PLL along
with Spread Spectrum and VCXO technology to make it one of
the most versatile clock synthesizers in the market. The device
uses a Cypress-proprietary PLL to drive up to three configurable
outputs in an 8-pin SOIC.
The CY22801 is programmed with an easy-to-use programmer
dongle, the CY36800, in conjunction with the CyClocksRT™
software. This enables fast sample generation of prototype
builds for user-defined frequencies. Cypress’s value-added
distribution partners and third-party programming systems from
BP Microsystems, HiLo Systems, and others, can also be
contacted for large production quantities. A JEDEC file needs to
be configured to program CY22801, which can be generated
using the CyClocksRT™ software.
Logic Block Diagram
XIN/CLKIN
XOUT
SDAT/FS0/
VCXO/OE
/PD#
VCXO REF
VCXO with Logic
FS2
SCLK
/FS1
SDAT
/FS0
/PD#
Serial I/F
with
Control
Logic
OE
PLL
Divider
1
Divider
2
Switch
Matrix
CLKA
CLKB/
FS1/
SCLK
CLKC
/FS2
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15571 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 20, 2012