CY22701 Datasheet, PDF (6/15 Pages) Cypress Semiconductor – 1 PLL In-System Programmable Clock Generator

PRELIMINARY
CY22701
Table 8. PLL Post Divider Options
Address
D7
D6
OCH
47H
DIV1SRC
DIV2SRC
DIV1N(6)
DIV2N(6)
D5
DIV1N(5)
DIV2N(5)
D4
DIV1N(4)
DIV2N(4)
D3
DIV1N(3)
DIV2N(3)
D2
DIV1N(2)
DIV2N(2)
D1
DIV1N(1)
DIV2N(1)
D0
DIV1N(0)
DIV2N(0)
PLL Post Divider Options
The output of the VCO is routed through two independent
muxes, then to two divider banks to determine the final clock
output frequency. The mux determines if the clock signal
feeding into the divider banks is the calculated VCO frequency
or REF. There are 2 select muxes (DIV1SRC and DIV2SRC)
and 2 divider banks (Divider Bank 1 and Divider Bank 2) used
to determine this clock signal. The clock signals passing
through DIV1SRC and DIV2SRC are referred to as DIV1CLK
and DIV2CLK, respectively.
The divider banks have 4 unique divider options available: /2,
/3, /4, and /DIVxN. DIVxN is a variable that can be indepen-
dently programmed (DIV1N and DIV2N) for each of the 2
divider banks. The minimum value of DIVxN is 4. The
maximum value of DIVxN is 127. A value of DIVxN below 4 is
not guaranteed to work properly.
DIV1SRC is a single bit variable, controlled by register OCH.
The remaining 7 bits of register OCH determine the value of
post divider DIV1N.
DIV2SRC is a single bit variable, controlled by register 47H.
The remaining 7 bits of register 47H determine the value of
post divider DIV2N.
Register OCH and 47H are defined in Table 8.
Charge Pump Settings [40H(2..0)]
are dependent on internal variable PB (see section [00H to
08H] – Reserved [0AH to 0BH] – Reserved [0DH to 10H]
–Reserved [14H to 3FH] –Reserved [43H to 44H] –Reserved
[48H to FFH] –Reserved [46H] –Reserved on page 7). Table 9
summarizes the proper charge pump settings, based on P_total.
See Table 10, Register 40H Change Pump Bit Settings on
page 6, for register 40H bit locations.
Although using Table 10 will guarantee stability, it is recom-
mended to use the Print Preview function in CyberClocks™ to
determine the ideal charge pump settings for optimal jitter
performance.
PLL stability cannot be guaranteed for P_total values below 16
and above 1023. If P_total values above 1023 are needed, use
CyberClocks to determine the best charge pump setting.
Table 9. Charge Pump Settings
Charge Pump Setting
– Pump(2..0)
000
Calculated P_total
16–44
001
45–479
010
480–639
011
640–799
100
800–1023
101, 110, 111
Do Not Use – device will be unstable
The correct pump setting is important for PLL stability. Charge
pump settings are controlled by bits (4..2) of register 40H, and
Table 10.Register 40H Change Pump Bit Settings
Address
D7
D6
D5
D4
D3
D2
D1
D0
40H
1
1
0
Pump(2) Pump(1) Pump(0)
PB(9)
PB(8)
Document #: 38-07698 Rev. *B
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