CY22701 Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 1 PLL In-System Programmable Clock Generator

PRELIMINARY
CY22701
1 PLL In-System Programmable Clock Generator
Features
• In-system programmable through I²C Serial
Programming Interface (SPI)
• Programmable SRAM and non-volatile EEPROM
memory bits with 3.3V supply
• Integrated, phase-locked loop with programmable P
and Q counters, output dividers
• Low-jitter, high-accuracy outputs
• 3.3V Operation
• 8-lead SOIC
Benefits
• Custom timing solutions for designs not suitable for
factory custom silicon, Xtals, or ASICs for production
• Program and optimize designs while chip is on system
board
• Programming voltages contained in chip
• High-performance PLL enables control of output
frequencies that are customizable to support a wide
range of applications
• Meets critical timing requirements in complex system
designs
• Meets industry-standard voltage platforms
• Industry standard packaging saves on board space
Part Number
CY22701
No. of Outputs
Input Frequency Range
Output Frequency Range
2
1 – 167 MHz (Driven Clock Input) {Commercial} 80 kHz – 200 MHz (3.3V) {Commercial}
1 –150 MHz (Driven Clock Input) {Industrial}
80 kHz –167 MHz (3.3V) {Industrial}
8 – 30 MHz (Crystal Reference) {Comm. or Ind.}
Logic Block Diagram
XIN
XOUT
[I²C- SPI:]
WP
SCL
SDAT
OSC
Q
Φ
VCO
P
PLL
Clock
Configuration
EEPROM
Memory Array
VDD VSS
OUTPUT
DIVIDERS
Output
Crosspoint
Switch
Array
CLK1
CLK2
Pin Configuration
XIN 1
VDD 2
SDA ₃
VSS 4
8 XOUT
7 CLK2/WP
6 CLK1
5 SCL
8 PIN SOIC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07698 Rev. *B
Revised February 8, 2005