CY14B256Q1_13 Datasheet, PDF (6/29 Pages) Cypress Semiconductor – 256-Kbit (32 K x 8) Serial (SPI) nvSRAM

CY14B256Q1
CY14B256Q2
CY14B256Q3
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The device STOREs data to the
nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated,
read/write
to
CY14B256Q1/CY14B256Q2/CY14B256Q3 is inhibited until the
cycle is completed.
The HSB signal or the RDY bit in the Status Register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (V_CAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from V_CC to
charge the capacitor connected to the V_CAP pin. When the
voltage on the V_CC pin drops below V_SWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the V_CAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since the last
RECALL.
Note If a capacitor is not connected to V_CAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
specified in AutoStore Enable (ASENB) instruction on page 15.
If AutoStore is enabled without a capacitor on the V_CAP pin, the
device attempts an AutoStore operation without sufficient charge
to complete the STORE. This corrupts the data stored in the
nvSRAM and Status Register. To resume normal functionality,
the WRSR instruction must be issued to update the nonvolatile
bits BP0, BP1 and WPEN in the Status Register.
Figure 3 shows the proper connection of the storage capacitor
(V_CAP) for AutoStore operation. Refer to DC Electrical
Characteristics on page 17 for the size of the V_CAP.
Note CY14B256Q1 does not support AutoStore operation. The
user must perform Software STORE operation by using the SPI
STORE instruction to secure the data.
Figure 3. AutoStore Mode
V_CC
0.1 uF
V_CC
CS
V_CAP
V_SS
V_CAP
Software STORE Operation
Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction irrespective of whether a write
has been performed since the last NV operation.
A STORE cycle takes t_STORE time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status Register or the HSB pin may be polled to find the
ready or busy status of the nvSRAM. After the t_STORE cycle time
is completed, the SRAM is activated again for read and write
operations.
Hardware STORE and HSB Pin Operation
The HSB pin in CY14B256Q3 is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, nvSRAM conditionally
initiates a STORE operation after t_DELAY duration. An actual
STORE cycle starts only if a write to the SRAM is performed
since the last STORE or RECALL cycle. Reads and writes to the
memory are inhibited for t_STORE duration or as long as HSB pin
is LOW.
The HSB pin also acts as an open drain driver (internal 100 k
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t_HHHD) with standard output high
current and then remains HIGH by an internal 100 k pull-up
resistor.
Note For successful last data byte STORE, a hardware store
should be initiated at least one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for t_LZHSB time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
Document Number: 001-53882 Rev. *J
Page 6 of 29