CY14B256Q1_13 Datasheet, PDF (15/29 Pages) Cypress Semiconductor – 256-Kbit (32 K x 8) Serial (SPI) nvSRAM

CY14B256Q1
CY14B256Q2
CY14B256Q3
Figure 14. Burst Mode Write Instruction Timing
CS
SCK
SI
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7 0 7 0 1 2 3 4 5 6 7
Data Byte 1
Data Byte N
Op-Code
15-bit Address
0 0 0 0 0 0 1 0 X 14 13 12 11 10 9 8
MSB
3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
LSB
SO
HI-Z
nvSRAM Special Instructions
CY14B256Q1/CY14B256Q2/CY14B256Q3 provides four
special instructions which enables access to the nvSRAM
specific functions: STORE, RECALL, ASDISB, and ASENB.
Table 7 lists these instructions.
Table 7. nvSRAM Special Instructions
Function Name
STORE
RECALL
ASENB
ASDISB
Opcode
0011 1100
0110 0000
0101 1001
0001 1001
Operation
Software STORE
Software RECALL
AutoStore Enable
AutoStore Disable
Software STORE (STORE) instruction
When a STORE instruction is executed, nvSRAM performs a
Software STORE operation. The STORE operation is performed
irrespective of whether a write has taken place since the last
STORE or RECALL operation.
To issue this instruction, the device must be write enabled (WEN
bit = ‘1’). The instruction is performed by transmitting the STORE
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the STORE
instruction.
Figure 15. Software STORE Operation
CS
SCK
012 34567
SI
00111100
SO
HI-Z
Software RECALL (RECALL) instruction
When a RECALL instruction is executed, nvSRAM performs a
Software RECALL operation. To issue this instruction, the device
must be write enabled (WEN = ‘1’).
The instruction is performed by transmitting the RECALL opcode
on the SI pin following the falling edge of CS. The WEN bit is
cleared on the positive edge of CS following the RECALL
instruction.
Figure 16. Software RECALL Operation
CS
SCK
01234567
SI
01100000
SO
HI-Z
AutoStore Enable (ASENB) instruction
The AutoStore Enable instruction enables the AutoStore on
CY14B256Q1. This setting is not nonvolatile and needs to be
followed by a STORE sequence if this is desired to survive the
power cycle.
To issue this instruction, the device must be write enabled
(WEN = ‘1’). The instruction is performed by transmitting the
ASENB opcode on the SI pin following the falling edge of CS.
The WEN bit is cleared on the positive edge of CS following the
ASENB instruction.
Note If ASDISB and ASENB instructions are executed in
CY14B256Q1, the device is busy for the duration of software
sequence processing time (t_SS). However, ASDISB and ASENB
instructions have no effect on CY14B256Q1 as AutoStore is
internally disabled.
Document Number: 001-53882 Rev. *J
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