CYRF69213_12 Datasheet, PDF (59/85 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69213
Endpoint 0 Mode
Because both firmware and the SIE are allowed to write to the Endpoint 0 Mode and Count Registers the SIE provides an interlocking
mechanism to prevent accidental overwriting of data.
When the SIE writes to these registers they are locked and the processor cannot write to them until after it has read them. Writing to
this register clears the upper four bits regardless of the value written.
Table 83. Endpoint 0 Mode (EP0MODE) [0x44] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Setup IN Received
OUT
ACK’d Trans
Received
Received
Mode[3:0]
Read/Write R/C[3]
R/C[3]
R/C[3]
R/C[3]
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit 7
SETUP Received
This bit is set by hardware when a valid SETUP packet is received. It is forced HIGH from the start of the data packet
phase of the SETUP transactions until the end of the data phase of a control write transfer and cannot be cleared dur-
ing this interval. While this bit is set to ‘1’, the CPU cannot write to the EP0 FIFO. This prevents firmware from over-
writing an incoming SETUP transaction before firmware has a chance to read the SETUP data
This bit is cleared by any non-locked writes to the register
0 = No SETUP received
1 = SETUP received
Bit 6
IN Received
This bit, when set, indicates a valid IN packet has been received. This bit is updated to ‘1’ after the host acknowl-
edges an IN data packet.When clear, it indicates that either no IN has been received or that the host didn’t acknowl-
edge the IN data by sending an ACK handshake
This bit is cleared by any non-locked writes to the register.
0 = No IN received
1 = IN received
Bit 5
OUT Received
This bit, when set, indicates a valid OUT packet has been received and ACKed. This bit is updated to ‘1’ after the last
received packet in an OUT transaction. When clear, it indicates no OUT received
This bit is cleared by any non-locked writes to the register
0 = No OUT received
1 = OUT received
Bit 4
ACK’d Transaction
The ACK’d transaction bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes
with a ACK packet
This bit is cleared by any non-locked writes to the register
1 = The transaction completes with an ACK
0 = The transaction does not complete with an ACK
Bits 3:0
Mode [3:0]
The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The mode
controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of
host packets to the endpoint
Document Number: 001-07552 Rev. *G
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