CYRF69213_12 Datasheet, PDF (43/85 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69213
Table 56. P1.3 Configuration (P13CR) [0x10] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Reserved Int Enable Int Act Low 3.3 V Drive High Sink Open Drain
Pull up
Enable
Output
Enable
Read/Write
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
This register controls the operation of the P1.3 pin. This register exists in all CYRF69213 parts
The P1.3 GPIO’s threshold is always set to TTL
When the SPI hardware is enabled, the output enable and output state of the pin is controlled by the SPI circuitry. When the SPI
hardware is disabled, the pin is controlled by the Output Enable bit and the corresponding bit in the P1 data register
Regardless of whether the pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3 V Drive, High Sink, Open Drain, and
Pull up Enable control the behavior of the pin
The 50 mA sink drive capability is only available in the CY7C638xx.
Table 57. P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
SPI Use
Int Enable Int Act Low 3.3 V Drive High Sink Open Drain
Pull up
Enable
Output
Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
These registers control the operation of pins P1.4–P1.6, respectively
The P1.4–P1.6 GPIO’s threshold is always set to TTL
When the SPI hardware is enabled, pins that are configured as SPI Use have their output enable and output state controlled by the
SPI circuitry. When the SPI hardware is disabled or a pin has its SPI Use bit clear, the pin is controlled by the Output Enable bit and
the corresponding bit in the P1 data register
Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3 V Drive, High Sink, Open Drain, and
Pull up Enable control the behavior of the pin
Bit 7
SPI Use
0 = Disable the SPI alternate function. The pin is used as a GPIO
1 = Enable the SPI function. The SPI circuitry controls the output of the pin
Important Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see Table 61)
When configured for SPI (SPI Use = 1 and Comm Modes [1:0] = SPI Master or SPI Slave mode), the input/output direction of pins
P1.3, P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input/output direction is NOT automatically set; it
must be explicitly set by firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4
must be configured as an input
Table 58. P1.7 Configuration (P17CR) [0x14] [R/W]
Bit #
7
6
5
4
3
2
1
Field
Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain
Pull up
Enable
Read/Write
–
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
This register controls the operation of pin P1.7. This register only exists in CY7C638xx
The 50 mA sink drive capability is only available in the CY7C638xx. The P1.7 GPIO’s threshold is always set to TTL
0
Output
Enable
R/W
0
Document Number: 001-07552 Rev. *G
Page 43 of 85