CY8C54 Datasheet, PDF (59/93 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC)

PRELIMINARY
PSoC^®5: CY8C54 Family Data Sheet
Table 11-3. AC Specifications^[9]
Parameter
Description
Conditions
F_CPU
F_busclk
Svdd
CPU frequency
Bus frequency
Vdd ramp rate
1.71V ≤ Vddd ≤ 5.5V
1.71V ≤ Vddd ≤ 5.5V
Tio_init
Time from Vddd/Vdda/Vccd/Vcca ≥
IPOR to I/O ports set to their reset
states
Tstartup
Vcca/Vdda = regulated from
Vdda/Vddd, no PLL used, fast boot
Time from Vddd/Vdda/Vccd/Vcca ≥ _mode
PPOR to CPU executing code at
reset vector
Vcca/Vccd = regulated from
Vdda/Vddd, no PLL used, slow boot
mode
Tsleep
Wakeup from limited active mode -
Application of external interrupt to
beginning of execution of next CPU
instruction
Thibernate
Wakeup form hibernate mode -
Application of external interrupt to
beginning of execution of next CPU
instruction
External reset pulse width
Min
DC
DC
1.00E-04
-
-
-
-
-
1
Typ
Max Units
-
80
MHz
-
80
MHz
-
1.00E+06 V/ms
-
10
µs
-
9
µs
-
36
µs
-
12
µs
-
100
µs
-
-
µs
Notes
8. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective data sheets, available in
PSoC Creator, the integrated design environment. To compute total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device data sheet and component data sheets.
9. Based on device characterization (Not production tested).
Document Number: 001-55036 Rev. *A
Page 59 of 93
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