CY8C54 Datasheet, PDF (19/93 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC)

PRELIMINARY
PSoC^®5: CY8C54 Family Data Sheet
6. System Integration
6.1 Clocking System
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL can generate up
to a 80 MHz clock, accurate to ±1% over voltage and temper-
ature. Additional internal and external clock sources allow each
design to optimize accuracy, power, and cost. All of the system
clock sources can be used to generate other clock frequencies
in the 16-bit clock dividers and throughout the device for anything
the user wants, for example a UART baud rate generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows designers to build clocking
systems with minimal input. The designer can specify desired
clock frequencies and accuracies, and the software locates or
builds a clock that meets the required specifications. This is
possible because of the programmability inherent PSoC.
Key features of the clocking system include:
„ Seven general purpose clock sources
‡ 3 to 80 MHz IMO ±1% at 3 MHz
‡ 4 to 33 MHz External Crystal Oscillator (MHzECO)
‡ DSI signal from an external I/O pin or other logic
‡ 24 to 80 MHz fractional Phase-Locked Loop (PLL) sourced
from IMO, MHzECO, or DSI
‡ Clock Doubler
‡ 1 kHz, 33 kHz, 100 kHz ILO for Watch Dog Timer (WDT) and
Sleep Timer
‡ 32.768 kHz External Crystal Oscillator (kHzECO) for Real
Time Clock (RTC)
‡ 36 MHz fixed clock (available only during test mode)
„ Dedicated 48 MHz Internal Oscillator for USB that auto locks
to USB bus clock requiring no external crystal for USB. (USB
equipped parts only)
„ Independently sourced clock dividers in all clocks
„ Eight 16-bit clock dividers for the digital system
„ Four 16-bit clock dividers for the analog system
„ Dedicated 16-bit divider for the CPU bus and CPU clock
„ Automatic clock configuration in PSoC Creator
Table 6-1. Oscillator Summary
Source
IMO
Fmin
Tolerance at Fmin
3 MHz ±1% over voltage and temperature
MHzECO
4 MHz Crystal dependent
DSI
PLL
Doubler
ILO
kHzECO
0 MHz
24 MHz
12 MHz
1 kHz
32 kHz
Input dependent
Input dependent
Input dependent
-30%, +65%
Crystal dependent
Fmax
80 MHz
33 MHz
Tolerance at Fmax
±5%
Crystal dependent
33 MHz
80 MHz
48 MHz
100 kHz
32 kHz
Input dependent
Input dependent
Input dependent
-20%, +30%
Crystal dependent
Startup Time
10 µs max
5 ms typ, max is
crystal dependent
Input dependent
250 µs max
1 µs max
1000 µs max
500 ms typ, max is
crystal dependent
Document Number: 001-55036 Rev. *A
Page 19 of 93
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