CYW43364 Datasheet, PDF (54/68 Pages) Cypress Semiconductor – Single-band 2.4 GHz IEEE 802.11b/g/n

PRELIMINARY
CYW43364
11.2 3.3V LDO (LDO3P3)
Table 23. LDO3P3 Specifications
Specification
Input supply voltage, V_in
Output current
Nominal output voltage, V_o
Dropout voltage
Output voltage DC accuracy
Quiescent current
Line regulation
Load regulation
PSRR
LDO turn-on time
External output capacitor, C_o
External input capacitor
Notes
Min. Typ.
Min. = V_o + 0.2V = 3.5V dropout voltage
requirement must be met under maximum load 3.1
3.6
for performance specifications.
–
0.001
–
Default = 3.3V.
–
3.3
At max. load.
–
–
Includes line/load regulation.
–5
–
No load
–
66
V_in from (V_o + 0.2V) to 4.8V, max. load
load from 1 mA to 450 mA
–
–
–
–
V_in ≥ V_o + 0.2V,
V_o = 3.3V, C_o = 4.7 µF,
Max. load, 100 Hz to 100 kHz
20
–
Chip already powered up.
–
160
Ceramic, X5R, 0402,
(ESR: 5 mΩ–240 mΩ), ± 10%, 10V
1.0^b
4.7
For SR_VDDBATA5V pin (shared with band
gap) Ceramic, X5R, 0402,
(ESR: 30m-200 mΩ), ± 10%, 10V.
–
4.7
Not needed if sharing VBAT capacitor 4.7 µF
with SR_VDDBATP5V.
Max.
4.8^a
450
–
200
+5
85
3.5
0.3
–
250
5.64
–
Units
V
mA
V
mV
%
µA
mV/V
mV/mA
dB
µs
µF
µF
a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as
high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.
Document Number: 002-14781 Rev. *C
Page 54 of 68