CY7C68014A Datasheet, PDF (53/62 Pages) Cypress Semiconductor – EZ-USB FX2LP™ USB Microcontroller High Speed USB Peripheral Controller

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
10.17.4 Sequence Diagram of a Single and Burst Asynchronous Write
Figure 34. Slave FIFO Asynchronous Write Sequence and Timing Diagram^[20]
t_SFA
t_FAH
FIFOADR
t_SFA
t_FAH
t=0
t_WRpwl t_WRpwh
T=0
t_WRpwl t_WRpwh
t_WRpwl t_WRpwh
t_WRpwl t_WRpwh
SLWR
t =1
t=3
T=1
T=3
T=4
T=6
T=7
T=9
SLCS
FLAGS
DATA
PKTEND
t_XFLG
t_SFD t_FDH
N
t=2
t_SFD t_FDH
N+1
T=2
t_SFD t_FDH
N+2
T=5
t_SFD t_FDH
N+3
T=8
t_XFLG
t_PEpwl
t_PEpwh
Figure 34 shows the timing relationship of the SLAVE FIFO write
in an asynchronous mode. The diagram shows a single write
followed by a burst write of 3 bytes and committing the 4 byte
short packet using PKTEND.
■ At t = 0 the FIFO address is applied, insuring that it meets the
setup time of t_SFA. If SLCS is used, it must also be asserted
(SLCS may be tied low in some applications).
■ At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of t_WRpwl and minimum de-active pulse width of
t_WRpwh. If the SLCS is used, it must be asserted with SLWR or
before SLWR is asserted.
■ At t = 2, data must be present on the bus t_SFD before the
deasserting edge of SLWR.
■ At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then increments the FIFO pointer.
The FIFO flag is also updated after t_XFLG from the deasserting
edge of SLWR.
The same sequence of events are shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note In the burst write mode, after SLWR is deasserted, the data
is written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post incre-
mented.
In Figure 34 after the four bytes are written to the FIFO and
SLWR is deasserted, the short 4 byte packet can be committed
to the host using the PKTEND. The external device should be
designed to not assert SLWR and the PKTEND signal at the
same time. It should be designed to assert the PKTEND after
SLWR is deasserted and met the minimum deasserted pulse
width. The FIFOADDR lines have to held constant during the
PKTEND assertion.
Document #: 38-08032 Rev. *M
Page 53 of 62
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