CY7C68014A Datasheet, PDF (39/62 Pages) Cypress Semiconductor – EZ-USB FX2LP™ USB Microcontroller High Speed USB Peripheral Controller

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
10.3 Data Memory Read
CLKOUT^[17]
A[15..0]
RD#
CS#
OE#
D[7..0]
CLKOUT^[17]
A[15..0]
t_CL
t_AV
t_CL
t_AV
Figure 13. Data Memory Read Timing Diagram
Stretch = 0
t_AV
t_STBL
t_STBH
t_SCSL
t_SOEL
[19]
t_ACC1
t_DSU
t_DH
data in
Stretch = 1
RD#
CS#
D[7..0]
Table 16. Data Memory Read Parameters
Parameter
t_CL
Description
1/CLKOUT Frequency
t_AV
t_STBL
t_STBH
t_SCSL
t_SOEL
t_DSU
t_DH
Delay from Clock to Valid Address
Clock to RD LOW
Clock to RD HIGH
Clock to CS LOW
Clock to OE LOW
Data Setup to Clock
Data Hold Time
t_ACC1^[19]
t_DSU
t_DH
data in
Min
Typ
Max
20.83
41.66
83.2
10.7
11
11
13
11.1
9.6
0
Unit
Notes
ns
48 MHz
ns
24 MHz
ns
12 MHz
ns
ns
ns
ns
ns
ns
ns
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either
RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for
which is based on the stretch value
Note
19. t_ACC2 and t_ACC3 are computed from the above parameters as follows:
t_ACC2(24 MHz) = 3*t_CL – t_AV –t_DSU = 106 ns
t_ACC2(48 MHz) = 3*t_CL – t_AV – t_DSU = 43 ns
t_ACC3(24 MHz) = 5*t_CL – t_AV –t_DSU = 190 ns
t_ACC3(48 MHz) = 5*t_CL – t_AV – t_DSU = 86 ns.
Document #: 38-08032 Rev. *M
Page 39 of 62
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