CY7C64713_11 Datasheet, PDF (53/72 Pages) Cypress Semiconductor – EZ-USB FX1 USB Microcontroller Full Speed USB Peripheral Controller

CY7C64713
Slave FIFO Synchronous Read
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 19. Slave FIFO Synchronous Read Timing Diagram
t_IFCLK
IFCLK
SLRD
FLAGS
t_SRD
t_RDH
t_XFLG
DATA
SLOE
N
t_OEon
N+1
t_XFD
t_OEoff
The following table provides the Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK. ^[35]
Table 15. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
Parameter
Description
t_IFCLK
t_SRD
t_RDH
t_OEon
t_OEoff
t_XFLG
t_XFD
IFCLK Period
SLRD to Clock Setup Time
Clock to SLRD Hold Time
SLOE Turn on to FIFO Data Valid
SLOE Turn off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
Min
Max
Unit
20.83
–
ns
18.7
–
ns
0
–
ns
–
10.5
ns
–
10.5
ns
–
9.5
ns
–
11
ns
The following table provides the Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK.^[35]
Table 16. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
Parameter
Description
t_IFCLK
t_SRD
t_RDH
t_OEon
t_OEoff
t_XFLG
t_XFD
IFCLK Period
SLRD to Clock Setup Time
Clock to SLRD Hold Time
SLOE Turn on to FIFO Data Valid
SLOE Turn off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
Min
Max
Unit
20.83
200
ns
12.7
–
ns
3.7
–
ns
–
10.5
ns
–
10.5
ns
–
13.5
ns
–
15
ns
Note
35. IFCLK must not exceed 48 MHz.
Document Number: 38-08039 Rev. *J
Page 53 of 72
[+] Feedback