CY7C64713_11 Datasheet, PDF (14/72 Pages) Cypress Semiconductor – EZ-USB FX1 USB Microcontroller Full Speed USB Peripheral Controller

CY7C64713
I²C Interface Boot Load Access
At power on reset the I²C interface boot loader loads the
VID/PID/DID configuration bytes and up to 16 KBytes of
program/data. The available RAM spaces are 16 KBytes from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051
is in reset. I²C interface boot loads only occur after power on
reset.
I²C Interface General Purpose Access
The 8051 can control peripherals connected to the I²C bus using
the I2CTL and I2DAT registers. FX1 provides I²C master control
only, because it is never an I²C slave.
Compatible with Previous Generation EZ-USB FX2
The EZ-USB FX1 is fit, form, and function upgradable to the
EZ-USB FX2LP. This makes for an easy transition for designers
wanting to upgrade their systems from full speed to high speed
designs. The pinout and package selection are identical, and all
firmware developed for the FX1 function in the FX2LP with
proper addition of high speed descriptors and speed switching
code.
Pin Assignments
Figure 7 on page 15 identifies all signals for the three package
types. The following pages illustrate the individual pin diagrams,
plus a combination diagram showing which of the full set of
signals are available in the 128, 100, and 56-pin packages.
The signals on the left edge of the 56-pin package in Figure 7 on
page 15 are common to all versions in the FX1 family. Three
modes are available in all package versions: Port, GPIF master,
and Slave FIFO. These modes define the signals on the right
edge of the diagram. The 8051 selects the interface mode using
the IFCONFIG[1:0] register bits. Port mode is the power on
default configuration.
The 100-pin package adds functionality to the 56-pin package by
adding these pins:
■ PORTC or alternate GPIFADR[7:0] address signals
■ PORTE or alternate GPIFADR[8] address signal and seven
additional 8051 signals
■ Three GPIF Control signals
■ Four GPIF Ready signals
■ Nine 8051 signals (two USARTs, three timer inputs, INT4,and
INT5#)
■ BKPT, RD#, WR#.
The 128-pin package adds the 8051 address and data buses
plus control signals. Note that two of the required signals, RD#
and WR#, are present in the 100-pin version. In the 100-pin and
128-pin versions, an 8051 control bit is set to pulse the RD# and
WR# pins when the 8051 reads from and writes to the PORTC.
Document Number: 38-08039 Rev. *J
Page 14 of 72
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