CY8C38_1105 Datasheet, PDF (52/130 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) Multiply and divide instructions

PSoC^® 3: CY8C38 Family
Data Sheet
Figure 8-1. Analog Subsystem Block Diagram
DAC
A
DAC
N
A
L
O
GPIO G
Port
R
O
U
T
I
N
G
Precision
Reference
SC/CT Block
SC/CT Block
SC/CT Block
SC/CT Block
CMP
Comparators
CMP CMP CMP
CapSense Subsystem
DAC
DAC
A
N
A
L
O
G ^GPIO
Port
R
O
U
T
I
N
G
Analog ^{Config &}
Interface
Status
Registers
PHUB
CPU
DSI
Array
Clock
Distribution
Decimator
The PSoC Creator software program provides a user friendly
interface to configure the analog connections between the GPIO
and various analog resources and connections from one analog
resource to another. PSoC Creator also provides component
libraries that allow you to configure the various analog blocks to
perform application specific functions (PGA, transimpedance
amplifier, voltage DAC, current DAC, and so on). The tool also
generates API interface libraries that allow you to write firmware
that allows the communication between the analog peripheral
and CPU/Memory.
8.1 Analog Routing
The CY8C38 family of devices has a flexible analog routing
architecture that provides the capability to connect GPIOs and
different analog blocks, and also route signals between different
analog blocks. One of the strong points of this flexible routing
architecture is that it allows dynamic routing of input and output
connections to the different analog blocks.
For information on how to make pin selections for optimal analog
routing, refer to the application note, AN58304 - PSoC® 3 and
PSoC® 5 - Pin Selection for Analog Designs.
„ Each GPIO is connected to one analog global and one analog
mux bus
„ Eight analog local buses (abus) to route signals between the
different analog blocks
„ Multiplexers and switches for input and output selection of the
analog blocks
8.1.2 Functional Description
Analog globals (AGs) and analog mux buses (AMUXBUS)
provide analog connectivity between GPIOs and the various
analog blocks. There are 16 AGs in the CY8C38 family. The
analog routing architecture is divided into four quadrants as
shown in Figure 8-2. Each quadrant has four analog globals
(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is
connected to the corresponding AG through an analog switch.
The analog mux bus is a shared routing resource that connects
to every GPIO through an analog switch. There are two
AMUXBUS routes in CY8C38, one in the left half (AMUXBUSL)
and one in the right half (AMUXBUSR), as shown in Figure 8-2
on page 53.
8.1.1 Features
„ Flexible, configurable analog routing architecture
„ 16 analog globals (AG) and two analog mux buses
(AMUXBUS) to connect GPIOs and the analog blocks
Document Number: 001-11729 Rev. *S
Page 52 of 130
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