CY8C38_1105 Datasheet, PDF (50/130 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) Multiply and divide instructions

PSoC^® 3: CY8C38 Family
Data Sheet
7.7 Timers, Counters, and PWMs
The timer/counter/PWM peripheral is a 16-bit dedicated
peripheral providing three of the most common embedded
peripheral features. As almost all embedded systems use some
combination of timers, counters, and PWMs. Four of them have
been included on this PSoC device family. Additional and more
advanced functionality timers, counters, and PWMs can also be
instantiated in UDBs as required. PSoC Creator allows you to
choose the timer, counter, and PWM features that they require.
The tool set utilizes the most optimal resources available.
The timer/counter/PWM peripheral can select from multiple clock
sources, with input and output signals connected through the
DSI routing. DSI routing allows input and output connections to
any device pin and any internal digital signal accessible through
the DSI. Each of the four instances has a compare output,
terminal count output (optional complementary compare output),
and programmable interrupt request line. The
Timer/Counter/PWMs are configurable as free running, one shot,
or Enable input controlled. The peripheral has timer reset and
capture inputs, and a kill input for control of the comparator
outputs. The peripheral supports full 16-bit capture.
Timer/Counter/PWM features include:
„ 16-bit Timer/Counter/PWM (down count only)
„ Selectable clock source
„ PWM comparator (configurable for LT, LTE, EQ, GTE, GT)
„ Period reload on start, reset, and terminal count
„ Interrupt on terminal count, compare true, or capture
„ Dynamic counter reads
„ Timer capture mode
„ Count while enable signal is asserted mode
„ Free run mode
„ One Shot mode (stop at end of period)
„ Complementary PWM outputs with deadband
„ PWM output kill
7.8 I²C
The I²C peripheral provides a synchronous two wire interface
designed to interface the PSoC device with a two wire I²C serial
communication bus. The bus is compliant with Philips ‘The I²C
Specification’ version 2.1. Additional I²C interfaces can be
instantiated using Universal Digital Blocks (UDBs) in PSoC
Creator, as required.
To eliminate the need for excessive CPU intervention and
overhead, I²C specific support is provided for status detection
and generation of framing bits. I²C operates as a slave, a master,
or multimaster (Slave and Master). In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I²C interfaces through DSI
routing and allows direct connections to any GPIO or SIO pins.
I²C provides hardware address detect of a 7-bit address without
CPU intervention. Additionally the device can wake from
low-power modes on a 7-bit hardware address match. If wakeup
functionality is required, I²C pin connections are limited to the
two special sets of SIO pins.
I²C features include:
„ Slave and master, transmitter, and receiver operation
„ Byte processing for low CPU overhead
„ Interrupt or polling CPU interface
„ Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
„ 7 or 10-bit addressing (10-bit addressing requires firmware
support)
„ SMBus operation (through firmware support - SMBus
supported in hardware in UDBs)
„ 7-bit hardware address compare
„ Wake from low-power modes on address match
Figure 7-21. Timer/Counter/PWM
Clock
Reset
Enable
Capture
Kill
Timer / Counter /
PWM 16-bit
IRQ
TC / Compare!
Compare
Data transfers follow the format shown in Figure 7-22. After the
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'
indicates a request for data (READ). A data transfer is always
terminated by a STOP condition (P) generated by the master.
However, if a master still wishes to communicate on the bus, it
can generate a repeated START condition (Sr) and address
another slave without first generating a STOP condition. Various
combinations of read/write formats are then possible within such
a transfer.
Figure 7-22. I²C Complete Transfer Timing
SDA
SCL
START
Condition
1-7
ADDRESS
8
9
R/W
ACK
Document Number: 001-11729 Rev. *S
1-7
8
DATA
9
ACK
1-7
8
DATA
9
ACK
STOP
Condition
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