CY8C3246AXI-138T Datasheet, PDF (51/128 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family Data Sheet
Figure 7-9. Digital System Interconnect
T im ers
C o u n te rs
I2C
Interrupt
C o n tro lle r
DMA
C o n tro lle r
IO Port
Pins
G lobal
C locks
Digital System Routing I/F
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
the master clock (see Figure 6-1). Normally all inputs from pins
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
Figure 7-11. I/O Pin Synchronization Routing
UDB ARRAY
Digital System Routing I/F
G lobal
C lo c ks
I/O Port
Pins
E M IF
D e l-S ig
DAC
C om parators
DO
DI
Figure 7-12. I/O Pin Output Connectivity
8 IO Data Output Connections from the
UDB Array Digital System Interface
Interrupt and DMA routing is very flexible in the CY8C32
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design. Figure 7-10 shows the structure of the IDMUX
(Interrupt/DMA Multiplexer).
Figure 7-10. Interrupt and DMA Processing in the IDMUX
Interrupt and DMA Processing in IDMUX
Fixed Function IRQs
IRQs
UDB Array
DRQs
Fixed Function DRQs
Edge
Detect
Edge
Detect
0
1
Interrupt
Controller
2
3
DMA termout (IRQs)
0
1
DMA
Controller
2
DO
DO
DO
DO
DO
DO
DO
DO
PIN 0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7
Port i
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
Figure 7-13. I/O Pin Output Enable Connectivity
4 IO Control Signal Connections from
UDB Array Digital System Interface
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
OE
PIN 0
OE
PIN1
OE
PIN2
OE
PIN3
OE
PIN4
OE
PIN5
OE
PIN6
OE
PIN7
Port i
Document Number: 001-56955 Rev. *Y
Page 51 of 128