CY8C3246AXI-138T Datasheet, PDF (29/128 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family Data Sheet
Table 6-1. Oscillator Summary
Source
IMO
MHzECO
Fmin
3 MHz
4 MHz
Tolerance at Fmin
±2% over voltage and temperature
Crystal dependent
DSI
PLL
Doubler
ILO
0 MHz
24 MHz
48 MHz
1 kHz
Input dependent
Input dependent
Input dependent
–50%, +100%
kHzECO
32 kHz Crystal dependent
Fmax
24 MHz
25 MHz
Tolerance at Fmax
±4%
Crystal dependent
33 MHz
50 MHz
48 MHz
100 kHz
Input dependent
Input dependent
Input dependent
–55%, +100%
32 kHz Crystal dependent
3-24 MHz
IMO
4-25 MHz
ECO
Figure 6-1. Clocking Subsystem
External IO
or DSI
0-33 MHz
32 kHz ECO
1,33,100 kHz
ILO
Startup Time
13-µs max
5 ms typ, max is
crystal dependent
Input dependent
250 µs max
1 µs max
15 ms max in lowest
power mode
500 ms typ, max is
crystal dependent
48 MHz
Doubler for
USB
24-50 MHz
PLL
Master
Mux
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
CPU Clock Divider
4 bit
CPU
Clock
Bus Clock Divider
16 bit
Bus
Clock
s
Analog Clock k
Divider 16 bit e
w
s
Analog Clock k
Divider 16 bit e
w
7
s
Analog Clock k
Divider 16 bit e
w
s
Analog Clock k
Divider 16 bit e
w
Document Number: 001-56955 Rev. *Y
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