CY8C34_1105 Datasheet, PDF (50/127 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) DC to 50 MHz operation

PSoC^® 3: CY8C34 Family
Data Sheet
I²C features include:
„ Slave and Master, Transmitter, and Receiver operation
„ Byte processing for low CPU overhead
„ Interrupt or polling CPU interface
„ Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
„ 7 or 10-bit addressing (10-bit addressing requires firmware
support)
„ SMBus operation (through firmware support – SMBus
supported in hardware in UDBs)
„ 7-bit hardware address compare
„ Wake from low-power modes on address match
Data transfers follow the format shown in Figure 7-22. After the
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'
indicates a request for data (READ). A data transfer is always
terminated by a STOP condition (P) generated by the master.
However, if a master still wishes to communicate on the bus, it
can generate a repeated START condition (Sr) and address
another slave without first generating a STOP condition. Various
combinations of read/write formats are then possible within such
a transfer.
Figure 7-22. I²C Complete Transfer Timing
SDA
SCL
START
Condition
1-7
ADDRESS
8
9
R/W
ACK
1-7
8
DATA
9
ACK
1-7
8
DATA
9
ACK
STOP
Condition
8. Analog Subsystem
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
„ Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses.
„ High resolution Delta-Sigma ADC.
„ Two 8-bit DACs that provide either voltage or current output.
„ Four comparators with optional connection to configurable LUT
outputs.
„ Two configurable switched capacitor/continuous time (SC/CT)
blocks for functions that include opamp, unity gain buffer,
programmable gain amplifier, transimpedance amplifier, and
mixer.
„ Two opamps for internal use and connection to GPIO that can
be used as high current output buffers.
„ CapSense subsystem to enable capacitive touch sensing.
„ Precision reference for generating an accurate analog voltage
for internal analog blocks.
Document Number: 001-53304 Rev. *L
Page 50 of 127