CY8C34_1105 Datasheet, PDF (106/127 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) DC to 50 MHz operation

PSoC^® 3: CY8C34 Family
Data Sheet
EM_ Clock
EM_ CEn
EM_ Addr
EM_ OEn
EM_ Data
EM_ ADSCn
Figure 11-64. Synchronous Read Cycle Timing
Tcp/2
Tceld
Tcehd
Taddrv
Toeld
Taddriv
Address
Toehd
Tadscld
Tds
Data
Tadschd
Table 11-62. Synchronous Read Cycle Specifications
Parameter
Description
T
EMIF clock period^[47]
Tcp/2
EM_Clock pulse high
Tceld
EM_CEn low to EM_Clock high
Tcehd
EM_Clock high to EM_CEn high
Taddrv EM_Addr valid to EM_Clock high
Taddriv EM_Clock high to EM_Addr invalid
Toeld
EM_OEn low to EM_Clock high
Toehd
EM_Clock high to EM_OEn high
Tds
Data valid before EM_OEn high
Tadscld EM_ADSCn low to EM_Clock high
Tadschd EM_Clock high to EM_ADSCn high
Conditions
Vdda ≥ 3.3 V
Min
Typ
30.3
–
T/2
–
5
–
T/2 – 5
–
5
–
T/2 – 5
–
5
–
T
–
T + 15
–
5
–
T/2 – 5
–
Max
Units
–
nS
–
nS
–
nS
–
nS
–
nS
–
nS
–
nS
–
nS
–
nS
–
nS
–
nS
Note
47. Limited by GPIO output frequency, see Table 11-10 on page 75.
Document Number: 001-53304 Rev. *L
Page 106 of 127