W194 Datasheet, PDF (5/6 Pages) Cypress Semiconductor – Frequency Multiplier and Zero Delay Buffer

W194
AC Electrical Characteristics: T_A = 0°C to +70°C, V_DD = 3.3V ±5%
Parameter
Description
Test Condition
Min
Typ
Max
Unit
f_IN
Input Frequency^[1]
OUT2 = REF
f_OUT
Output Frequency
OUT1 15-pF load^[6]
10
MHz
133
MHz
t_R
Output Rise Time
2.0V to 0.8V, 15-pF load
3.5
ns
t_F
Output Fall Time
2.0V to 0.8V, 15-pF load
2.5
ns
t_ICLKR
Input Clock Rise Time^[2]
10
ns
t_ICLKF
Input Clock Fall Time^[2]
10
ns
t_PD
FBIN to REF Skew^{[3, 4]}
Measured at V_DD/2
–2
0.6
2
ns
t_D
Duty Cycle
15-pF load^[5]
40
50
60
%
t_LOCK
PLL Lock Time
Power supply stable
1.0
ms
t_JC
Jitter, Cycle-to-Cycle
300
ps
AC Electrical Characteristics: T_A = 0°C to +70°C, V_DD = 5.0V ±10%
Parameter
Description
Test Condition
Min
Typ
Max
Unit
f_IN
Input Frequency^[1]
OUT2 = REF
f_OUT
Output Frequency
OUT1 15-pF load^[6]
10
MHz
133
MHz
t_R
Output Rise Time
2.0V to 0.8V, 15-pF load
2.5
ns
t_F
Output Fall Time
2.0V to 0.8V, 15-pF load
1.5
ns
t_ICLKR
Input Clock Rise Time^[2]
10
ns
t_ICLKF
Input Clock Fall Time^[2]
10
ns
t_PD
FBIN to REF Skew^{[3, 4]}
Measured at V_DD/2
–2
0.6
2
ns
t_D
Duty Cycle
15-pF load^{[5, 7]}
40
50
60
%
t_LOCK
PLL Lock Time
Power supply stable
1.0
ms
t_JC
Jitter, Cycle-to-Cycle
200
ps
Notes:
1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration).
2. Longer input rise and fall time will degrade skew and jitter performance.
3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.
4. Skew is measured at 1.4V on rising edges.
5. Duty cycle is measured at 1.4V.
6. For the higher drive -11, the load is 20 pF.
7. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case.
Ordering Information
Ordering Code
W194
Document #: 38-00794-A
Option
-70
Package
Name
G
Package Type
8-pin SOIC (150-mil)
5