W194 Datasheet, PDF (2/6 Pages) Cypress Semiconductor – Frequency Multiplier and Zero Delay Buffer

W194
Pin Definitions
Pin Name
IN
FBIN
Pin No.
2
1
OUT1
6
OUT2
8
VDD
7
GND
3
FS0:1
4, 5
Pin
Type
I
I
O
O
P
P
I
Pin Description
Reference Input: The output signals will be synchronized to this signal.
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure
proper functionality. If the trace between FBIN and the output pin being used for feedback
is equal in length to the traces between the outputs and the signal destinations, then the
signals received at the destinations will be synchronized to the REF signal input (IN).
Output 1: The frequency of the signal provided by this pin is determined by the feedback
signal connected to FBIN, and the FS0:1 inputs (see Table 1).
Output 2: The frequency of the signal provided by this pin is one-half of the frequency of
OUT1. See Table 1.
Power Connections: Connect to 3.3V or 5V. This pin should be bypassed with a 0.1-µF
decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter perfor-
mance.
Ground Connection: Connect all grounds to the common system ground plane.
Function Select Inputs: Tie to V_DD (HIGH, 1) or GND (LOW, 0) as desired per Table 1.
Overview
The W194-70 is a two-output zero delay buffer and frequency
multiplier. It provides an external feedback path allowing max-
imum flexibility when implementing the Zero Delay feature.
This is explained further in the sections of this data sheet titled
“How to Implement Zero Delay,” and “Inserting Other Devices
in Feedback Path.”
The W194-70 is a pin-compatible upgrade of the Cypress
W42C70-01. The W194-70 addresses some application de-
pendent problems experienced by users of the older device.
C_A
G
10 µF
Ferrite
Bead
C8
0.01 µF
V+ ^{Power Supply Connection}
G
FBIN
IN
GND
FS0
1
2
3
G
4
OUT 2
8
V_DD
7
OUT 1
6
5
22Ω
OUTPUT 2
C9 = 0.1 µF
G
22Ω
OUTPUT 1
FS1
Figure 1. Schematic/Suggested Layout
2