CYRF69103_11 Datasheet, PDF (5/68 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power 16-bit free running timer

CYRF69103
6.6 SDR Mode
Table 6-2. SDR Mode
Register
TX_CFG_ADR
RX_CFG_ADR
XACT_CFG_ADR
FRAMING_CFG_ADR
TX_OVERRIDE_ADR
RX_OVERRIDE_ADR
ANALOG_CTRL_ADR
DATA64_THOLD_ADR
EOP_CTRL_ADR
PREAMBLE_ADR
Value
0X3E
0X4B
0X05
0X00
0X04
0X14
0X01
0X07
0xA1
0xAAAA09
Description
64 chip PN code, SDR mode, PA = 6
AGC is enabled. LNA and attenuator are disabled. Fast turnaround is disabled,
the device uses high side receive injection and Hi-Lo is disabled. Overwrite to
receive buffer is enabled and RX buffer is configured to receive eight bytes
maximum. Enables RXOW to allow new packets to be loaded into the receive
buffer. This also enables the VALID bit which is used by the first generation
radio’s error correction firmware.
AutoACK is disabled. Forcing end state is disabled. The device is configured to
transition to Idle mode after Receive or Transmit. ACK timeout is set to 128 µs.
All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is
needed.
Disable Transmit CRC-16.
The receiver rejects packets with a zero seed. The RX CRC-16 checker is
disabled and the receiver accepts bad packets that do not match the seed in
the CRC_seed registers. This helps in communication with the first generation
radio that does not have CRC capabilities.
Set ALL SLOW. When set, the synthesizer settle time for all channels is the
same as the slow channels in the first generation radio, for manual ACK
consistency
Sets the number of allowed corrupted bits to 7 which is close to the recom-
mended 12% value.
Sets the number of consecutive symbols for non-correlation to detect end of
packet.
AAAA are the two preamble bytes. Any other byte can also be written into the
preamble register file. Recommended counts of the preamble bytes to be sent
must be >8.
Document #: 001-07611 Rev *F
Page 5 of 68
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