CYRF69103_11 Datasheet, PDF (47/68 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power 16-bit free running timer

CYRF69103
Table 19-17. SPI SCLK Frequency
20. Timer Registers
SCLK CPUCLK
Select Divisor
SCLK Frequency when
CPUCLK = 12 MHz
00
6 2 MHz
01
12 1 MHz
10
48 250 kHz
11
96 125 kHz
19.7 SPI Interface Pins
The SPI interface between the radio function and MCU function
uses pins P1.3–P1.5 and optionally P1.6. These pins are
configured using the P1.3 and P1.4–P1.6 Configuration.
All timer functions of the CYRF69103 are provided by a single
timer block. The timer block is asynchronous from the CPU clock.
The 16-bit free running counter is used as the time-base for timer
captures and can also be used as a general time-base by
software.
20.1 Registers
20.1.1 Free Running Counter
The 16-bit free running counter is clocked by a 4 or 6 MHz
source. It can be read in software for use as a general purpose
time base. When the low order byte is read, the high order byte
is registered. Reading the high order byte reads this register
allowing the CPU to read the 16-bit value atomically (loads all
bits at one time). The free running timer generates an interrupt
at 1024 μs rate. It can also generate an interrupt when the free
running counter overflow occurs—every 16.384 ms. This allows
extending the length of the timer in software.
Figure 20-1. 16-bit Free Running Counter Block Diagram
Timer Capture
C loc k
16-bit Free
Running Counter
O v e rflo w
Interrupt
1024-µs
T im e r
Interrupt
Table 20-1. Free Running Timer Low Order Byte (FRTMRL) [0x20] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Free Running Timer [7:0]
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bits 7:0 Free running Timer [7:0]
This register holds the low order byte of the 16-bit free running timer. Reading this register causes the high order byte to be
moved into a holding register allowing an automatic read of all 16 bits simultaneously.
For reads, the actual read occurs in the cycle when the low order is read. For writes the actual time the write occurs is the cycle
when the high order is written.
When reading the free running timer, the low order byte must be read first and the high order second. When writing, the low
order byte must be written first then the high order byte.
Document #: 001-07611 Rev *F
Page 47 of 68
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