CYP15G0101DXB_12 Datasheet, PDF (5/43 Pages) Cypress Semiconductor – Single-channel HOTLink II™ Transceiver

CYP15G0101DXB
CYV15G0101DXB
Pin Configuration
Top View
1
2
3
4
5
6
7
8
9
10
A
V_CC
IN2+
V_CC
OUT2– RXMODE TXMODE[1] IN1+
V_CC
OUT1–
V_CC
B
V_CC
IN2–
TDO
OUT2+ TXRATE TXMODE[0] IN1–
#NC^[2] OUT1+
V_CC
C
RFEN
LPEN
RXLE RXCLKC+ RXRATE SDASEL SPDSEL PARCTL RFMODE INSEL
D
BOE[0] BOE[1] FRAMCHAR GND
GND
GND
GND
TMS
TRSTZ
TDI
E
BISTLE DECMODE OELE
GND
GND
GND
GND
TCLK RXCKSEL TXCKSEL
F
RXST[2] RXST[1] RXST[0] GND
GND
GND
GND
TXPER REFCLK– REFCLK+
G
RXOP RXD[1] RXD[5]
GND
GND
GND
GND
TXOP TXCLKO+ TXCLKO–
H
RXD[0] RXD[2] RXD[6]
LFI
TXCT[1] TXD[6]
TXD[3]
TXCLK TXRST #NC^[2]
J
V_CC
RXD[3]
RXD[7] RXCLK– TXCT[0] TXD[5]
TXD[2]
TXD[0]
#NC^[2]
V_CC
K
V_CC
RXD[4]
V_CC
RXCLK+ TXD[7] TXD[4] TXD[1]
V_CC
SCSEL
V_CC
Bottom View
10
9
8
7
6
5
4
3
2
1
V_CC
OUT1–
V_CC
IN1+ TXMODE[1] RXMODE OUT2–
V_CC
IN2+
V_CC
A
V_CC
OUT1+
#NC^[2]
IN1– TXMODE[0] TXRATE OUT2+
TDO
IN2–
V_CC
B
INSEL RFMODE PARCTL SPDSEL SDASEL RXRATE RXCLKC+ RXLE
LPEN
RFEN
C
TDI
TRSTZ
TMS
GND
GND
GND
GND FRAMCHAR BOE[1] BOE[0]
D
TXCKSEL RXCKSEL TCLK
GND
GND
GND
GND
OELE DECMODE BISTLE
E
REFCLK+ REFCLK– TXPER
GND
GND
GND
GND RXST[0] RXST[1] RXST[2]
F
TXCLKO– TXCLKO+ TXOP
GND
GND
GND
GND
RXD[5] RXD[1] RXOP
G
#NC^[2] TXRST TXCLK
TXD[3]
TXD[6] TXCT[1]
LFI
RXD[6] RXD[2] RXD[0]
H
V_CC
#NC^[2]
TXD[0]
TXD[2]
TXD[5] TXCT[0] RXCLK– RXD[7]
RXD[3]
V_CC
J
V_CC
SCSEL
V_CC
TXD[1] TXD[4] TXD[7] RXCLK+
V_CC
RXD[4]
V_CC
K
Note
2. #NC = Do Not Connect.
Document Number: 38-02031 Rev. *N
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