CYP15G0101DXB_12 Datasheet, PDF (19/43 Pages) Cypress Semiconductor – Single-channel HOTLink II™ Transceiver

CYP15G0101DXB
CYV15G0101DXB
When RFMODE = MID (open), the Cypress-mode multi-byte
framer is selected. The required detection of multiple framing
characters makes the link much more robust to incorrect framing
due to aliased framing characters in the data stream. In this
mode, the framer does not adjust the character clock boundary,
but instead aligns the character to the already recovered
character clock. This ensures that the recovered clock does not
contain any significant phase changes or hops during normal
operation or framing, and allows the recovered clock to be
replicated and distributed to other external circuits or
components using PLL-based clock distribution elements. In this
framing mode, the character boundaries are only adjusted if the
selected framing character is detected at least twice within a
span of 50-bits, with both instances on identical 10-bit character
boundaries.
When RFMODE = HIGH, the alternate-mode multi-byte framer
is enabled. Like the Cypress-mode multi-byte framer, multiple
framing characters must be detected before the character
boundary is adjusted. In this mode, the framer does not adjust
the character clock boundary, but instead aligns the character to
the already recovered character clock. In this mode, the data
stream must contain a minimum of four of the selected framing
characters, received as consecutive characters, on identical
10-bit boundaries, before character framing is adjusted.
Framing is enabled when RFEN = HIGH. If RFEN = LOW, the
framer is disabled. When the framer is disabled, no changes are
made to the recovered character boundary, regardless of the
presence of framing characters in the data stream.
10B/8B Decoder Block
The decoder logic block performs three primary functions:
■ decoding the received transmission characters back into data
and special character codes
■ comparing generated BIST patterns with received characters
to permit at-speed link and device testing
■ generation of ODD parity on the decoded characters.
10B/8B Decoder
The framed parallel output of the deserializer shifter is passed to
the 10B/8B decoder where, if the decoder is enabled
(DECMODE  LOW), it is transformed from a 10-bit transmission
character back to the original data and special character codes.
This block uses the 10B/8B decoder patterns in Table 20 and
Table 21 of this data sheet. Valid data characters are indicated
by a 000b bit-combination on the RXST[2:0] status bits, and
special character codes are indicated by a 001b bit-combination
on these same status outputs. Framing characters, invalid
patterns, disparity errors, and synchronization status are
presented as alternate combinations of these status bits.
The 10B/8B decoder operates in two normal modes, and can
also be bypassed. The operating mode for the decoder is
controlled by the DECMODE input.
When DECMODE = LOW, the decoder is bypassed and raw
10-bit characters are passed to the output register. In this mode,
the receive elasticity buffers are bypassed, and RXCKSEL must
be MID.
When DECMODE = MID (or open), the 10-bit transmission
characters are decoded using Table 20 and Table 21. Received
special code characters are decoded using the Cypress column
of Table 21.
When DECMODE = HIGH, the 10-bit transmission characters
are decoded using Table 20 and Table 21. Received special
code characters are decoded using the alternate column of
Table 21.
Receive BIST Operation
The receiver interface contains an internal pattern generator that
can be used to validate both device and link operation. This
generator is enabled by the BOE[0] signal as listed in Table 8
(when the BISTLE latch enable input is HIGH). When enabled,
a register in the receive channel becomes a pattern generator
and checker by logically converting to a linear feedback shift
register (LFSR). This LFSR generates a 511-character
sequence that includes all data and special character codes,
including the explicit violation symbols. This provides a
predictable yet pseudo-random sequence that can be matched
to an identical LFSR in the attached transmitter. If the receive
channels are configured for REFCLK clocking
(RXCKSEL  LOW), each pass is preceded by a 16-character
Word Sync Sequence.
When synchronized with the received data stream, the receiver
checks each character in the decoder with each character
generated by the LFSR and indicates compare errors and BIST
status at the RXST[2:0] bits of the output register.
When the BISTLE signal is HIGH, if the BOE[0] input is LOW the
BIST generator/checker in the receive channel is enabled (and
if BOE[1] = LOW the BIST generator in the transmit channel is
enabled). When BISTLE returns LOW, the values of the
BOE[1:0] signals are captured in the BIST enable latch. These
values remain in the BIST enable latch until BISTLE is returned
high to open the latch again. All captured signals in the BIST
enable latch are set HIGH (i.e., BIST is disabled) following a
device reset (TRSTZ is sampled LOW).
When BIST is first recognized as being enabled in the receiver,
the LFSR is preset to the BIST-loop start-code of D0.0. This D0.0
character is sent only once per BIST loop. The status of the BIST
progress and any character mismatches is presented on the
RXST[2:0] status outputs.
Code rule violations or running disparity errors that occur as part
of the BIST loop do not cause an error indication. RXST[2:0]
indicates 010b or 100b for one character period per BIST loop to
indicate loop completion. This status can be used to check test
pattern progress. These same status values are presented when
the decoder is bypassed and BIST is enabled on the receive
channel.
The status reported on RXST[2:0] by the BIST state machine are
listed in Table 16. When receive BIST is enabled, the same
status is reported on the receive status outputs regardless of the
state of DECMODE.
The specific patterns checked by each receiver are described in
detail in the Cypress application note HOTLink Built-In Self-test.
The sequence compared by the CYP(V)15G0101DXB is
identical to that in the CY7B933 and CY7C924DX, allowing
interoperable systems to be built when used at compatible serial
signaling rates.
Document Number: 38-02031 Rev. *N
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