CYIWOSC1300AA Datasheet, PDF (5/31 Pages) Cypress Semiconductor – 1.3 Megapixel CMOS Sensor

PRELIMINARY
CYIWOSC1300AA
2.0 Functional Overview
The analog core of the chip is comprised of the actual image
sensor with its column amplifiers and addressing logic, and an
analog processing block with a Programmable Gain Amplifier
(PGA), and a 10-bit ADC. The column amplifiers perform
double sampling on the pixel signals, thus reducing fixed
pattern noise due to pixel non-uniformity.
The output of the column amplifiers is a single analog signal
stream of Bayer-colored pixels, which is sent to the PGA for
additional gain and offset conditioning. The single ADC
accepts this stream and turns it into a 10-bit digitized stream
of Bayer-colored pixel values.
The readout sequencer performs automated readout of
images with given exposure time and gain settings. Mirrored
readout and frame time adjustments are programmable.
Most of the chip's image readout parameters are doubled-up
into two separate records, allowing the user to change from
preview mode to snapshot and back in a minimum of time.
The output from the sensor is a Bayer pattern: alternate rows
are a sequence of either green/red pixels or blue/green pixels.
The offset and gain stages of the analog signal chain provide
per-color control of the pixel data.
Analog supply
2.65-3.1V
Digital supply
2.65-3.1V
Master clock
Standby
CMD_D
CMD_CLK
CMD_A
1uF
1kO
CLK
STANDBY
CMD_D
CMD_CLK
CMD_A
REG_BYPASS
VDD_28
VAA
VAA_PIX
10uF
1uF
1uF
RESET_N
VDDIO
AGND
PIX_OE_n
PIX_D[9: 0]
PIX_CLK
LINE
FRAME
FLASH
VDD_18_O
PIX_OE_n
PIX_D[9:0]
PIX_CLK
LINE
FRAME
FLASH
1uF
GND
DGND
Figure2-1 shows a typical module wiring diagram. When
using the on-chip regulator REG_BYPASS has to be
connected to ground. VDD_28 can be connected to a
2.65–3.1V supply like all other power supplies. There must be
sufficient decoupling on the supplies to insure clean supply
voltages. Note that RESET_N is typically connected with an
RC circuit to hold RESET_N low until all power supplies have
reached their proper level.
Analog supply Digital supply
2.65-3.1V
2.65-3.1V
Master clock
Standby
CMD_D
CMD_CLK
CMD_A
1.8V
1uF
1kO
CLK
STANDBY
CMD_D
CMD_CLK
CMD_A
REG_BYPASS
VDD_28
VAA
VAA_PIX
PIX_OE_n
PIX_D[9:0]
PIX_CLK
LINE
FRAME
FLASH
VDD_18_O
PIX_OE_n
PIX_D[9:0]
PIX_CLK
LINE
FRAME
FLASH
1uF
GND
10uF
1uF
1uF
RESET_N
VDDIO
AGND
DGND
Analog ground
Logic ground
Figure 2-2. Typical Configuration without On-chip
Regulator
Figure2-2 shows a typical module wiring diagram. When not
using the on-chip regulator REG_BYPASS and the VDD_28
have to be connected to their appropriate levels. VDD_28 has
to be connected to a 1.8V supply. There must be sufficient
decoupling on the supplies to insure clean supply voltages.
Note that RESET_N is typically connected with an RC circuit
to hold RESET_N low until all power supplies have reached
their proper level.
Analog ground
Logic ground
Figure 2-1. Typical Configuration using On-chip Regulator
Document #: 38-19008 Rev. *A
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