CYIWOSC1300AA Datasheet, PDF (10/31 Pages) Cypress Semiconductor – 1.3 Megapixel CMOS Sensor

PRELIMINARY
CYIWOSC1300AA
PIX_D bytes change state on a falling edge of PIX_CLK, and
are to be sampled on the rising edge, or vice versa, as
programmed by the user.
PIX_CLK is active for all physically scanned pixels (also for
dummy pixels) and is inactive during line blanking intervals.
PIX_CLK is a gated and possibly inverted copy of the internal
chip clock. In normal operation the internal clock is equal to the
system clock CLK, but in low-power operation the internal
clock, and thus PIX_CLK, can be divided by 2 or 4.
6.2 Frame Sequence Structure
6.2.1 Overview
The acquisition of a number of frames is an operation that is
started by the CCP (camera control processor), following
which the sequencer first initializes the sequence, then takes
the frames in a regular, periodic fashion, and (when needed)
terminates the sequence. The frame sequence itself can be
adorned by optional attributes such as blanking out of a
specific number of frames, blanking out of bad frames, Xenon
flash ignition between two frames, etc.
Within the sequence of frames will be specific synchronization
points for updating image-sensitive parameters such as
exposure time and gain, without disrupting the frame
sequence itself.
6.2.2 Frame Timelines Examples
The following timelines indicate a number of possible
scenarios. The lower/orange band in each diagram houses the
periods during which the lines of a frame are reset (top to
bottom), the upper/green band the periods during which the
lines are read out (top to bottom).
The frame size is kept constant (number of valid lines), but the
number of dummy lines is varied to demonstrate several
concepts of readout.
In Figure6-4, the shutter time is considerably shorter than the
frame time. A moderate amount of dummy lines is included,
extending the frame time somewhat.
As the diagram indicates, the acquisition of a sequence of
frames is a periodic, regular process: at all times is one line of
a particular frame being read, while a line belonging to that
same frame, or to the next frame, is being reset.
The one exception to this rule is during sequence initialization:
the first N lines (N corresponding to the desired exposure time)
of the first frame are reset, while no lines of frame 1 are being
read.
Figure6-5 illustrates a typical frame sequence with the
exposure/shutter time (almost) equal to the total frame time.
This increases the maximally-allowed exposure time much
more than in previous diagrams, while the frame rate is
severely reduced. It illustrates increased exposure time at the
cost of a lowered frame rate. This is only to be done when
sufficient light is lacking and when the camera is held stable.
6.3 Controlling the Sequencer
An image or sequence acquisition is started when a positive
edge is seen on the RUN bit in the CCP_CTRL register.
When CCP_CTRL is updated with a RUN transition from '0' to
'1' (or remains at '1', see AUTO_START bit), any present
image acquisition sequence is stopped (also see FAST_STOP
bit) and a new acquisition is started in a potentially new record
(see CTXT bit).
A frame sequence ends normally when the frame counter
(N_FRAMES) is at zero after the last (dummy) line of a frame
has been produced be the sequencer.
Deassertion of RUN at any time makes the sequencer finish
its present line, after which it stops scanning and enters its idle
state (also see FAST_STOP bit in the CCP _CTRL register).
Line reads per
frame
Line resets per
frame
Time
Frame 1
Dummy 1
Frame 2
Dummy 2
Frame 3
Dummy 3
Frame 1
Dummy 1
Frame 2
Dummy 2
Frame 3
Dummy 3
Shutter
time
Frame time
Figure 6-4. Typical Frame Sequence
Line reads per frame
Frame 1
Dummy 1
Line resets per frame
Frame 1
Dummy 1
Frame 2
Dummy 2 Dummy 2
Time
Shutter time
Frame time
Figure 6-5. Frame Sequence with Addition of a Very Large Number of Dummy Lines
Document #: 38-19008 Rev. *A
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