CYF2018V Datasheet, PDF (5/30 Pages) Cypress Semiconductor – 18/36/72-Mbit Programmable Multi-Queue FIFOs Independent read and write ports

CYF2018V, CYF2036V
CYF2072V
Pin Definitions
Pin Name
D[35:0]
Q[35:0]
WEN
REN
IE
OE
WCLK
RCLK
EF
FF
LD
RT
MRS
SPI_SCLK
SPI_SI
SPI_SEN
MARK
MB
WQSEL[2:0]
RQSEL[2:0]
TCK
TRST
TMS
TDI
TDO
DVal
I/O
Input
Output
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Pin Description
Data inputs: Data inputs for a 36-bit bus.
Data outputs: Data outputs for a 36-bit bus.
Write enable: WEN enables WCLK to write data into the FIFO memory and configuration registers.
Read enable: REN enables RCLK to read data from the FIFO memory and configuration registers.
Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data
input pins. If it is enabled, data on the D[35:0] pins is written into the FIFO. The internal write address
pointer is always incremented at rising edge of WCLK if WEN is enabled, regardless of the IE level. This
is used for ‘write masking’ or incrementing the write pointer without writing into a location.
Output enable: When OE is LOW, FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs
are in High Z (high impedance) state.
Write clock: When enabled by WEN, the rising edge of WCLK writes data into the FIFO if LD is high and
into the configuration registers if LD is low.
Read clock: When enabled by REN, the rising edge of RCLK reads data from the FIFO memory if LD is
high and from the configuration registers if LD is low.
Empty flag: When EF is LOW, the Queue is empty. EF is synchronized to RCLK.
Full flag: When FF is LOW, the Queue is full. FF is synchronized to WCLK.
Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When
LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO.
Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO which
is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed
data is read and the read pointer is incremented until it is equal to the write pointer.
Master reset: MRS initializes the read and write pointers to zero and sets the output register to all zeroes.
During Master Reset, the configuration registers are all set to default values and the flags are reset.
Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset
registers if SPI_SEN is enabled.
Serial input: Serial input when SPI_SEN is enabled.
Serial enable: Enables serial loading of programmable flag offsets and configuration registers.
Mark for retransmit: When this pin is asserted the current location of the read pointer is marked. Any
subsequent retransmit operation resets the read pointer to this position.
Mailbox: When asserted the reads and writes happen to flow-through mailbox register.
Write Queue select: Select maximum eight Queues using pins.
Read Queue select: Select maximum eight Queues using pins.
Test clock (TCK) pin for JTAG.
Reset pin for JTAG.
Test mode select (TMS) pin for JTAG.
Test data in (TDI) pin for JTAG.
Test data out (TDO) for JTAG.
Data valid: Active low data valid signal to indicate valid data on Q[35:0].
Document Number: 001-68336 Rev. **
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