CYF2018V Datasheet, PDF (25/30 Pages) Cypress Semiconductor – 18/36/72-Mbit Programmable Multi-Queue FIFOs Independent read and write ports

Figure 22. Mark
CYF2018V, CYF2036V
CYF2072V
RCLK
REN
MARK
RQSEL[2:0]
0
Q[35:0] Q (N-2) Q (N-1)
Q (N)
Q (N+1) Q (N+2) Q (N+3)
Q (N+4) Q (N+5)
Q (N+6)
DVal
DATA MARKED IN QUE-0
QVal[2:0]
0
RCLK
REN
RT_FL
RQSEL[2:0]
Q[35:0]
DVal
QVal[2:0]
Figure 23. Retransmit
t_PRT
L_{RT_TO_REN}
L_{RT_TO_DATA}
0
Q (N)
Q (N+1)
RETRANSMIT FROM
DATA MARKED IN QUE-0
0
Document Number: 001-68336 Rev. **
Page 25 of 30
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