CY7C343B_04 Datasheet, PDF (5/11 Pages) Cypress Semiconductor – 64-Macrocell MAX® EPLD

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CY7C343B
INPUT
INPUT
DELAY
t_IN
PIA
DELAY
t_PIA
EXPANDER
DELAY
t_EXP
LOGIC ARRAY
CONTROL DELAY t_CLR
t_LAC
t_PRE
LOGIC ARRAY
DELAY
t_LAD
t_RSU
t_RH
SYSTEM CLOCK DELAY t_ICS
CLOCK
DELAY
t_IC
REGISTER
t_RD
t_COMB
t_LATCH
OUTPUT
DELAY
t_OD
t_XZ
t_ZX
INPUT/
OUTPUT
FEEDBACK
DELAY
t_FD
I/O DELAY
t_IO
Figure 1. CY7C343B Internal Timing Model
External Synchronous Switching Characteristics Over Operating Range
Parameter
Description
t_PD1
Dedicated Input to Combinatorial Output Com’l/Ind
Delay^[4]
t_PD2
I/O Input to Combinatorial Output Delay^[4] Com’l/Ind
t_SU
Global clock setup time
Com’l/ Ind
t_CO1
Synchronous Clock Input to Output Delay^[3] Com’l/Ind
t_H
Input Hold Time from Synchronous Clock Com’l/Ind
Input
t_WH
t_WL
f_MAX
t_CNT
t_ODH
f_CNT
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency^[5]
Minimum Global Clock Period
Output Data Hold Time After Clock
Maximum Internal Global Clock
Frequency^[6]
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Notes:
4. C1 = 35 pF.
5. The f_MAX values represent the highest frequency for pipeline data.
6. This parameter is measured with a 16-bit counter programmed into each LAB.
7C343B-25
Min. Max.
25
40
15
14
0
8
8
62.5
20
2
50
7C343B-30
Min. Max.
30
45
20
16
0
10
10
50
25
2
40
7C343B-35
Min. Max. Unit
35 ns
55 ns
25
ns
20 ns
0
ns
12.5
ns
12.5
ns
40
MHz
30 ns
2
ns
33.3
MHz
Document #: 38-03038 Rev. *B
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