CY7C343B_04 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 64-Macrocell MAX® EPLD

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CY7C343B
Features
• 64 MAX macrocells in 4 LABs
• 8 dedicated inputs, 24 bidirectional I/O pins
• Programmable interconnect array
• Advanced 0.65-micron CMOS technology to increase
performance
• Available in 44-pin HLCC, PLCC
• Lowest power MAX device
64-Macrocell MAX® EPLD
Functional Description
The CY7C343B is a high-performance, high-density erasable
programmable logic device, available in 44-pin PLCC and
HLCC packages.
The CY7C343B contains 64 highly flexible macrocells and 128
expander product terms. These resources are divided into four
Logic Array Blocks (LABs) connected through the Program-
mable Inter-connect Array (PIA). There are 8 input pins, one
that doubles as a clock pin when needed. The CY7C343B also
has 28 I/O pins, each connected to a macrocell (6 for LABs A
and C, and 8 for LABs B and D). The remaining 36 macrocells
are used for embedded logic.
The CY7C343B is excellent for a wide range of both
synchronous and asynchronous applications.
Logic Block Diagram
9 INPUT
11 INPUT
12 INPUT
13 INPUT
2
4
I/O PINS
5
6
7
8
LAB A
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
DEDICATED INPUTS
SYSTEM CLOCK
MACROCELLS 7 - 16
P
LAB B
I
15
MACROCELL 17
16
MACROCELL 18
A
17
MACROCELL 19
I/O PINS
18
19
MACROCELL 20
MACROCELL 21
20
MACROCELL 22
22
MACROCELL 23
23
MACROCELL 24
MACROCELLS 25 - 32
(3, 14, 25, 36)
(10, 21, 32, 43)
V_CC
GND
INPUT 35
INPUT/CLK 34
INPUT 33
INPUT 31
LAB D
MACROCELL 56
MACROCELL 55
MACROCELL 54
MACROCELL 53
MACROCELL 52
MACROCELL 51
MACROCELL 50
MACROCELL 49
MACROCELLS57 - 64
LAB C
MACROCELL 38
MACROCELL 37
MACROCELL 36
MACROCELL 35
MACROCELL 34
MACROCELL 33
MACROCELLS39 - 48
1
44
42
41
I/O PINS
40
39
38
37
30
29
28
I/O PINS
27
26
24
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03038 Rev. *B
Revised April 9, 2004