CY7C197N_11 Datasheet, PDF (5/13 Pages) Cypress Semiconductor – 256 K × 1 Static RAM CMOS for optimum speed/power

CY7C197N
Figure 2. AC Test Loads and Waveforms^[5]
5V
OUTPUT
R1 329
5V
OUTPUT
R1 329 
30 pF
INCLUDING
JIG AND
SCOPE
R2
202 
5 pF
R2
255 
(255 MIL) INCLUDING
(255 MIL)
JIG AND
(a)
SCOPE _(b)
3.0 V
10%
GND
< t_r
Equivalent to: THÉVENIN EQUIVALENT
125 
OUTPUT
1.90 V
Commercial
ALL INPUT PULSES
90%
90%
10%
< t_r
Switching Characteristics
Over the Operating Range^[6]
Parameter
Description
READ CYCLE
t_RC
t_AA
t_OHA
t_ACE
t_LZCE
t_HZCE
t_PU
t_PD
WRITE CYCLE^[9]
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_SD
t_HD
t_LZWE
t_HZWE
Read cycle time
Address to data valid
Output hold from address change
CE LOW to data valid
CE LOW to low Z^[7]
CE HIGH to high Z^{[7, 8]}
CE LOW to power-up
CE HIGH to power-down
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE HIGH to low Z^[7]
WE LOW to high Z^{[7, 8]}
-25
Unit
Min
Max
25
–
ns
–
25
ns
3
–
ns
–
25
ns
3
–
ns
0
11
ns
0
–
ns
–
20
ns
25
–
ns
20
–
ns
20
–
ns
0
–
ns
0
–
ns
20
–
ns
15
–
ns
0
–
ns
3
–
ns
0
11
ns
Notes
5. t_r = < 5 ns for the -25 and slower speeds.
6. Test conditions assume signal transition time of 5 ns or less for -25 and slower speeds, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output
loading of the specified I_OL/I_OH and 30-pF load capacitance.
7. At any given temperature and voltage condition, t_HZCE is less than t_LZCE and t_HZWE is less than t_LZWE for any given device.
8. t_HZCE and t_HZWE are specified with C_L = 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 001-06495 Rev. *D
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