CY7C197N_11 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 256 K × 1 Static RAM CMOS for optimum speed/power

CY7C197N
256 K × 1 Static RAM
256 K × 1 Static RAM
Features
■ High speed
❐ 25 ns
■ CMOS for optimum speed/power
■ Low active power
❐ 880 mW
■ Low standby power
❐ 220 mW
■ Transistor-transistor logic (TTL)-compatible inputs and outputs
■ Automatic power-down when deselected
Functional Description
The CY7C197N is a high-performance CMOS static RAM
organized as 256 K words by 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and three-state
drivers. The CY7C197N has an automatic power-down feature,
reducing the power consumption by 75% when deselected.
Writing to the device is accomplished when the Chip Enable (CE)
and Write Enable (WE) inputs are both LOW. Data on the input
pin (D_IN) is written into the memory location specified on the
address pins (A₀ through A₁₇).
Reading the device is accomplished by taking chip enable (CE)
LOW while Write Enable (WE) remains HIGH. Under these
conditions the contents of the memory location specified on the
address pins will appear on the data output (D_OUT) pin.
The output pin stays in a high-impedance state when Chip
Enable (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C197N uses a die coat to insure alpha immunity.
Logic Block Diagram
DI
INPUT BUFFER
A₁₃
A₁₄
A₁₅
A₁₆
A₁₇
A₀
1024 x 256
A₁
ARRAY
A₂
A₃
A₄
COLUMN
DECODER
POWER
DOWN
A₅ A₆ A₇ A₈ A₉ A₁₀ A₁₁ A₁₂
DO
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-06495 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 1, 2011