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CY7C1311KV18_12 Datasheet, PDF (5/32 Pages) Cypress Semiconductor – 18-Mbit QDR® II SRAM Four-Word Burst Architecture
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CY7C1311KV18, CY7C1911KV18
CY7C1313KV18, CY7C1315KV18
Pin Configurations
The pin configurations for CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 follow. [1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1311KV18 (2 M × 8)
1
2
3
4
5
6
7
8
9
10
11
A
CQ NC/72M
A
WPS
NWS1
K NC/144M RPS
A
NC/36M CQ
B
NC
NC
NC
A NC/288M K
NWS0
A
NC
NC
Q3
C
NC
NC
NC
VSS
A
NC
A
VSS
NC
NC
D3
D
NC
D4
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
Q2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q1
D1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D0
N
NC
D7
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q7
A
A
C
A
A
NC
NC
NC
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CY7C1911KV18 (2 M × 9)
1
2
3
4
5
6
7
8
A
CQ NC/72M
A
WPS
NC
K NC/144M RPS
B
NC
NC
NC
A NC/288M K
BWS0
A
C
NC
NC
NC
VSS
A
NC
A
VSS
D
NC
D5
NC
VSS
VSS
VSS
VSS
VSS
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS
VDDQ
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
G
NC
D6
Q6
VDDQ
VDD
VSS
VDD
VDDQ
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS
VDDQ
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
N
NC
D8
NC
VSS
A
A
A
VSS
P
NC
NC
Q8
A
A
C
A
A
R
TDO
TCK
A
A
A
C
A
A
Note
1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
9
10
11
A
NC/36M CQ
NC
NC
Q4
NC
NC
D4
NC
NC
NC
NC
D3
Q3
NC
NC
NC
NC
NC
NC
VDDQ
VREF
ZQ
NC
Q2
D2
NC
NC
NC
NC
NC
Q1
NC
NC
D1
NC
NC
NC
NC
D0
Q0
A
TMS
TDI
Document Number: 001-58904 Rev. *E
Page 5 of 32
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