CY7C1303AV18 Datasheet, PDF (5/20 Pages) Cypress Semiconductor – 18-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture

PRELIMINARY
CY7C1303AV18
CY7C1306AV18
Read Operations
The CY7C1303AV18 is organized internally as two arrays of
512K x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting RPS active at the rising edge of the positive input
clock (K). The address is latched on the rising edge of the K
clock. Following the next K clock rise the corresponding lower
order 18-bit word of data is driven onto the Q_[17:0] using C as
the output timing reference. On the subsequent rising edge of
C the higher order data word is driven onto the Q_[17:0]. The
requested data will be valid 2.5 ns from the rising edge of the
output clock (C and C, or K and K when in single clock mode,
167-MHz device).
Synchronous internal circuitry will automatically three-state
the outputs following the next rising edge of the positive output
clock (C). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D_[17:0] is latched and stored into the
lower 18-bit Write Data register provided BWS_[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D_[17:0] is stored into the Write Data register
provided BWS_[1:0] are both asserted active. The 36 bits of data
are then written into the memory array at the specified
location.
When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1303AV18.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter-
mined by BWS₀ and BWS₁ which are sampled with each set
of 18-bit data words. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a Write will allow the data stored in the device for that byte
Application Example^[1]
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1303AV18 can be used with a single clock mode. In
this mode the device will recognize only the pair of input clocks
(K and K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-up.This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1303AV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor-
mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
Depth Expansion
The CY7C1303AV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the positive input clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V_SS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
V_DDQ = 1.5V. The output impedance is adjusted every 1024
cycles to account for drifts in supply voltage and temperature.
Note:
1. The above application shows 4 QDR-I being used.
Document #: 38-05492 Rev. *A
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