CY7C1303AV18 Datasheet, PDF (1/20 Pages) Cypress Semiconductor – 18-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture

PRELIMINARY
CY7C1303AV18
CY7C1306AV18
18-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture
Features
Functional Description
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz Clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball
(11x15 matrix)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
• Variable Impedance HSTL
Configurations
CY7C1303AV18 – 1M x 18
CY7C1306AV18 – 512K x 36
The CY7C1303AV18 and CY7C1306AV18 are 1.8V
Synchronous Pipelined SRAMs equipped with QDR™ archi-
tecture. QDR architecture consists of two separate ports to
access the memory array. The Read port has dedicated Data
Outputs to support Read operations and the Write Port has
dedicated Data inputs to support Write operations. Access to
each port is accomplished through a common address bus.
The Read address is latched on the rising edge of the K clock
and the Write address is latched on the rising edge of K clock.
QDR has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus required with
common I/O devices. Accesses to the CY7C1303AV18/
CY7C1306AV18 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with Double Data Rate (DDR) inter-
faces. Therefore, data can be transferred into the device on
every rising edge of both input clocks (K and K) and out of the
device on every rising edge of the output clock (C and C, or K
and K when in single clock mode) thereby maximizing perfor-
mance while simplifying system design. Each address location
is associated with two 18-bit words (CY7C1303AV18) or two
36-bit words (CY7C1306AV18) that burst sequentially into or
out of the device.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Selects allow each port to operate
independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1303AV18)
D_[17:0]
18
A_(18:0)
19
K
K
Address
Register
CLK
Gen.
Write
Data Reg
Write
Data Reg
512Kx18 512Kx18
Memory Memory
Array
Array
Read Data Reg.
Address
Register
19 ^A(18:0)
Control
Logic
RPS
C
C
Vref
WPS
BWS₀
BWS₁
Control
Logic
36 ₁₈
18
Reg.
Reg.
Reg. ¹⁸
18
18
Q_[17:0]
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05492 Rev. *A
Revised June 1, 2004