CY7C024AV Datasheet, PDF (5/19 Pages) Cypress Semiconductor – 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Definitions
Left Port
CE_L
R/W_L
OE_L
A_0L–A_13L
I/O_0L–I/O_17L
SEM_L
UB_L
LB_L
INT_L
BUSY_L
M/S
V_CC
GND
NC
Right Port
CE_R
R/W_R
OE_R
A_0R–A_13R
I/O_0R–I/O_17R
SEM_R
UB_R
LB_R
INT_R
BUSY_R
Description
Chip Enable.
Read/Write Enable.
Output Enable.
Address (A₀–A₁₁ for 4K devices; A₀–A₁₂ for 8K devices; A₀–A₁₃ for
16K).
Data Bus Input/Output.
Semaphore Enable.
Upper Byte Select (I/O₈–I/O₁₅ for x16 devices; I/O₉–I/O₁₇ for x18
devices).
Lower Byte Select (I/O₀–I/O₇ for x16 devices; I/O₀–I/O₈ for x18
devices).
Interrupt Flag.
Busy Flag.
Master or Slave Select.
Power.
Ground.
No Connect.
Architecture
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV consist of an array of 4K, 8K, and 16K words of 16 and
18 bits each of dual-port RAM cells, I/O and address lines, and
control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in
memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. Two Interrupt
(INT) pins can be utilized for port-to-port communication. Two
Semaphore (SEM) control pins are used for allocating shared
resources. With the M/S pin, the devices can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The devices also have an automatic power-down
feature controlled by CE. Each port is provided with its own
output enable control (OE), which allows data to be read from
the device.
Functional Description
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV
/036AV are low-power CMOS 4K, 8K, and 16K ×16/18
dual-port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can
be utilized as standalone 16/18-bit dual-port static RAMs or
multiple devices can be combined in order to function as a
32/36-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 32/36-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Select (CE) pin.
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV are available in 100-pin Thin Quad Plastic Flatpacks
(TQFP).
Write Operation
Data must be set up for a duration of t_SD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summarized
in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t_DDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t_ACE after CE or t_DOE after
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Document #: 38-06052 Rev. *E
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