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CY7C024AV Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM | |||
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CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
Features
⢠True dual-ported memory cells which allow
simultaneous access of the same memory location
⢠4/8/16K à 16 organization (CY7C024AV/025AV/026AV)
⢠4/8K à 18 organization (CY7C0241AV/0251AV)
⢠16K à 18 organization (CY7C036AV)
⢠0.35-micron CMOS for optimum speed/power
⢠High-speed access: 20 and 25 ns
⢠Low operating power
â Active: ICC = 115 mA (typical)
â Standby: ISB3 = 10 µA (typical)
Logic Block Diagram
R/WL
UBL
⢠Fully asynchronous operation
⢠Automatic power-down
⢠Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
⢠On-chip arbitration logic
⢠Semaphores included to permit software handshaking
between ports
⢠INT flag for port-to-port communication
⢠Separate upper-byte and lower-byte control
⢠Pin select for Master or Slave
⢠Commercial and industrial temperature ranges
⢠Available in 100-pin TQFP
R/WR
UBR
CEL
LBL
OEL
[1]
8/9
I/O8/9LâI/O15/17L
I/O0LâI/O[72/]8L
8/9
I/O
Control
I/O
Control
CER
LBR
OER
8/9
[1]
I/O8/9LâI/O15/17R
8/9
[2]
I/O0LâI/O7/8R
[3]
A0LâA11/1213L
12/13/14 Address
Decode
True Dual-Ported
RAM Array
[3]
A0LâA11/12/13L
CEL
OEL
R/WL
SEML [4]
BUSYL
INTL
UBL
LBL
12/13/14
Interrupt
Semaphore
Arbitration
M/S
Notes:
1. I/O8âI/O15 for x16 devices; I/O9âI/O17 for x18 devices.
2. I/O0âI/O7 for x16 devices; I/O0âI/O8 for x18 devices.
3. A0âA11 for 4K devices; A0âA12 for 8K devices; A0âA13 for 16K devices.
4. BUSY is an output in master mode and an input in slave mode.
Address 12/13/14
Decode
12/13/14
[3]
A0RâA11/12/13R
[3]
A0RâA11/12/13R
CER
OER
R/WR
[4] SEMR
BUSYR
INTR
UBR
LBR
Cypress Semiconductor Corporation ⢠3901 North First Street ⢠San Jose, CA 95134 ⢠408-943-2600
Document #: 38-06052 Rev. *E
Revised October 12, 2004
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