CY62128V Datasheet, PDF (5/12 Pages) Cypress Semiconductor – 128K x 8 Static RAM

CY62128V Family
Data Retention Current Graph (for “L” version only)
DATA RETENTION CURRENT
vs. SUPPLY VOLTAGE
80
70
60
50
40
30
T_A =25°C
20
10
0
SUPPLY VOLTAGE (V)
Switching Characteristics Over the Operating Range^[5]
62128V-55 62128V-70 62128V25-100 62128V18-200
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t_RC
Read Cycle Time
55
70
100
200
ns
t_AA
Address to Data Valid
55
70
100
200 ns
t_OHA
Data Hold from Address Change 5
10
10
10
ns
t_ACE
CE LOW to Data Valid
55
70
100
200 ns
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
OE LOW to Data Valid
OE LOW to Low Z^[6]
OE HIGH to High Z^{[6, 7]}
CE LOW to Low Z^[6]
CE HIGH to High Z^{[6, 7]}
20
35
75
125 ns
10
10
10
10
ns
20
25
50
75 ns
10
10
10
10
ns
20
25
50
75 ns
t_PU
CE LOW to Power-Up
0
0
0
0
ns
t_PD
CE HIGH to Power-Down
WRITE CYCLE^{[8, 9]}
55
70
100
200 ns
t_WC
Write Cycle Time
55
70
100
200
ns
t_SCE
CE LOW to Write End
45
60
100
190
ns
t_AW
Address Set-Up to Write End
45
60
100
190
ns
t_HA
Address Hold from Write End
0
0
0
0
ns
t_SA
Address Set-Up to Write Start
0
0
0
0
ns
t_PWE
WE Pulse Width
45
55
90
125
ns
t_SD
Data Set-Up to Write End
25
30
60
100
ns
t_HD
t_HZWE
t_LZWE
Data Hold from Write End
WE LOW to High Z^{[6, 7]}
WE HIGH to Low Z^[6]
0
0
0
0
ns
20
25
50
100 ns
5
5
10
15
ns
5. Test conditions assume signal transition time of 5 ns or less timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I_OL/I_OH and 100-pF load capacitance.
6. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
7. t_HZOE, t_HZCE, and t_HZWE are specified with C_L = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE₁ LOW, CE₂ HIGH, and WE LOW. CE₁ and WE signals must be LOW and CE₂ HIGH to initiate a
write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t_HZWE and t_SD.
5