CY62128V Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 128K x 8 Static RAM

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CY62128V Family
Features
• Low voltage range:
— 2.7V–3.6V (CY62128V)
— 2.3V–2.7V (CY62128V25)
— 1.6V–2.0V (CY62128V18)
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62128V family is composed of three high-performance
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE₁), an active HIGH Chip Enable (CE₂), an active
128K x 8 Static RAM
LOW Output Enable (OE) and three-state drivers. These de-
vices have an automatic power-down feature, reducing the
power consumption by over 99% when deselected. The
CY62128V family is available in the standard 450-mil-wide
SOIC, 32-lead TSOP-I, and STSOP packages.
Writing to the device is accomplished by taking Chip Enable
one (CE₁) and Write Enable (WE) inputs LOW and the Chip
Enable two (CE₂) input HIGH. Data on the eight I/O pins (I/O₀
through I/O₇) is then written into the location specified on the
address pins (A₀ through A₁₆).
Reading from the device is accomplished by taking Chip En-
able one (CE₁) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE₂) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
Logic Block Diagram
A₀
A₁
A₂
AA₃₄
A₅
A₆
AA₇₈
CE1
CE2
WE
OE
INPUT BUFFER
512x 256x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
62128V-1
Pin Configurations
Top View
SOIC
NC 1
A_{16 2}
A₁₄ 3
A₁₂ 4
A₇ 5
A₆ 6
A_{5 7}
A₄ 8
A₃ 9
A₂ 10
A_{1 11}
A₀ 12
I/O_{0 13}
I/O_{1 14}
I/O_{2 15}
GND ₁₆
32 VCC
31 A₁₅
30 CE₂
29 WE
28 _A13
27 _A8
26 _A9
25 _A11
24 _OE
23 A₁₀
22 CE₁
21 I/O7
20 ^I/O6
19 ^I/O5
18 ^I/O4
17 I/O₃
62128V-2
A₄
16
A₅
15
A₆
14
A₇
13
A₁₂
12
A₁₄
11
A₁₆
10
NC 9
V_CC
8
A₁₅
7
CE₂
6
WE
5
A₁₃
4
A₈
3
A₉
2
A₁₁
1
TSOP I
Reverse Pinout
Top View
(not to scale)
17 ^A3
18 ^A2
19 A1
20 A0
21 ^I/O0
22 ^I/O1
23 ^I/O2
24 GND
25 ^I/O3
26 ^I/O4
27 ^I/O5
28 ^I/O6
29 ^I/O7
30 ^CE1
31 ^A10
32 OE
62128V-3
A₁₁
1
A₉
2
A₈
3
A₁₃
4
WE
5
CE₂
6
A₁₅
7
V_CC
8
NC 9
A₁₆
10
A₁₄
11
A₁₂
12
A₇
13
A₆
14
A₅
15
A₄
16
TSOP I / STSOP
Top View
(not to scale)
32 OE
31 A₁₀
30 CE₁
29 I/O₇
28 I/O₆
27 I/O₅
26 I/O₄
25 I/O₃
24 GND
23 I/O₂
22 I/O₁
21 I/O₀
20 A₀
19 A₁
18 A₂
17 A₃
62128V-4
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 27, 2000