CY62128 Datasheet, PDF (5/8 Pages) Cypress Semiconductor – 128K x 8 Static RAM

PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (CE₁ or CE₂ Controlled)^[13,14]
ADDRESS
CE₁
CE₂
WE
DATA I/O
t_SA
t_AW
t_WC
t_SCE
t_PWE
t_SCE
t_SD
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)^[13,14]
ADDRESS
CE₁
t_WC
t_SCE
CE₂
WE
t_SCE
t_AW
t_SA
t_PWE
t_HA
t_HD
t_HA
OE
DATA I/O
NOTE 15
t_HZOE
t_SD
t_HD
DATA_IN VALID
Notes:
13. Data I/O is high impedance if OE = V_IH.
14. If CE₁ goes HIGH or CE₂ goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
CY62128
62128-7
62128-8
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