CY62128 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 128K x 8 Static RAM

1CY 621 28
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PRELIMINARY
CY62128
Features
• 4.5V − 5.5V operation
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
— 330 mW (max.) (60 mA)
• Low standby power (70 ns, LL version)
— 110 µW (max.) (20 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁, CE₂, and OE options
Functional Description
The CY62128 is a high-performance CMOS static RAM orga-
nized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE₁), an active HIGH
chip enable (CE₂), an active LOW output enable (OE), and
three-state drivers. This device has an automatic power-down
Logic Block Diagram
128K x 8 Static RAM
feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking chip enable
one (CE₁) and write enable (WE) inputs LOW and chip enable
two (CE₂) input HIGH. Data on the eight I/O pins (I/O₀ through
I/O₇) is then written into the location specified on the address
pins (A₀ through A₁₆).
Reading from the device is accomplished by taking chip en-
able one (CE₁) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE₂) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
The CY62128 is available in a standard 400-mil-wide SOJ,
525-mil wide (450-mil-wide body width) SOIC and 32-pin
TSOP type I.
Pin Configurations
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
CE₁
CE₂
WE
OE
INPUT BUFFER
512 x 256 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅ ^A11
A₉
1
2
A₈
3
I/O₆ A₁₃
4
WE
5
CE₂
6
I/O₇ A₁₅
7
62128-1
V_CC
8
NC
9
A₁₆
10
A₁₄
11
A₁₂
12
A₇
13
A₆
14
A₅
15
A₄
16
Top View
SOJ / SOIC
NC 1
A_{16 2}
A₁₄ 3
A₁₂ 4
A₇ 5
A₆ 6
A_{5 7}
A₄ 8
A₃ 9
A₂ 10
A_{1 11}
A₀ 12
I/O_{0 13}
I/O_{1 14}
I/O_{2 15}
GND ₁₆
32 VCC
31 A₁₅
30 CE₂
29 WE
28 _A13
27 _A8
26 _A9
25 _A11
24 _OE
23 A₁₀
22 CE₁
21 I/O7
20 ^I/O6
19 ^I/O5
18 ^I/O4
17 I/O₃
TSOP I
Top View
(not to scale)
32 OE
31
A₁₀
30 CE₁
29 I/O₇
28 I/O₆
27 I/O₅
26 _I/O4
25 I/O₃
24 GND
23 I/O₂
22 I/O₁
21 I/O₀
20 A₀
19 A₁
18 A₂
17 A₃
62128-2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 1996 - Revised November 1996