CY62126EV30 Datasheet, PDF (5/12 Pages) Cypress Semiconductor – 1-Mbit (64K x 16) Static RAM

CY62126EV30 MoBL^®
Switching Characteristics
Over the Operating Range ^{[10, 11]}
Parameter
Description
Read Cycle
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_PU
t_PD
t_DBE
t_LZBE
t_HZBE
Write Cycle ^[14]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z ^[12]
OE HIGH to High Z ^{[12, 13]}
CE LOW to Low Z ^[12]
CE HIGH to High Z ^{[12, 13]}
CE LOW to Power Up
CE HIGH to Power Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z ^[12]
BHE / BLE HIGH to High Z ^{[12, 13]}
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_BW
t_SD
t_HD
t_HZWE
t_LZWE
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
BHE / BLE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z ^{[12, 13]}
WE HIGH to Low Z ^[12]
45 ns (Industrial)
55 ns (Automotive)
Unit
Min
Max
Min
Max
45
55
ns
45
55
ns
10
10
ns
45
55
ns
22
25
ns
5
5
ns
18
20
ns
10
10
ns
18
20
ns
0
0
ns
45
55
ns
22
25
ns
5
5
ns
18
20
ns
45
55
ns
35
40
ns
35
40
ns
0
0
ns
0
0
ns
35
40
ns
35
40
ns
25
25
ns
0
0
ns
18
20
ns
10
10
ns
Notes
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V_CC(typ)/2, input pulse levels of 0 to V_CC(typ), and output loading of the
specified I_OL/I_OH and 30-pF load capacitance.
11. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
12. At any temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZBE is less than t_LZBE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any device.
13. t_HZOE, t_HZCE, t_HZBE, and t_HZWE transitions are measured when the outputs enter a high impedance state.
14. The internal write time of the memory is defined by the overlap of WE, CE = V_IL, BHE, BLE or both = V_IL. All signals must be active to initiate a write and any of
these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
Document #: 38-05486 Rev. *D
Page 5 of 12
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