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| CY29352_07 Datasheet, PDF (5/9 Pages) Cypress Semiconductor – 2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer | |||
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CY29352
AC Parameters[6] (VDD= 2.5V ± 5%, TA = â40°C to +85°C)
Parameter
Description
Condition
Min
tsk(B)
Bank-to-Bank Skew
Banks at same voltage, same
frequency
Banks at same voltage,
different frequency
tPLZ, HZ
tPZL, ZH
BW
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth
(â3 dB)
÷2 Feedback
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷12 Feedback
tJIT(CC)
Cycle-to-Cycle Jitter
Same frequency
Multiple frequencies
tJIT(PER)
Period Jitter
Same frequency
Multiple frequencies
tJIT(Ï)
I/O Phase Jitter
VCO < 300 MHz
VCO > 300 MHz
tLOCK
Maximum PLL Lock Time
AC Parameters[6] (VDD = 3.3V ± 5%, TA = â40°C to +85°C)
Parameter
Description
Condition
fVCO
fin
VCO Frequency
Input Frequency
÷2 Feedback
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷12 Feedback
Bypass mode (PLL_EN# = 1)
frefDC
tr , tf
fMAX
Input Duty Cycle
TCLK Input Rise/FallTime
Maximum Output Frequency
0.8V to 2.0V
÷2 Output
÷4 Output
÷6 Output
÷8 Output
÷12 Output
DC
Output Duty Cycle
fMAX < 100 MHz
fMAX > 100 MHz
tr , tf
Output Rise/Fall times
0.55V to 2.4V
t(Ï)
Propagation Delay (static phase TCLK to FB_IN, same VDD,
offset)
does not include jitter
tsk(O)
Output-to-Output Skew
Skew within each Bank
Min
200
100
50
33.33
25
16.67
0
25
100
50
33.33
25
16.67
48
44
0.1
â100
Typ
2
1 - 1.5
0.6
0.75
0.5
150
100
Typ
Document #: 38-07476 Rev. *A
Max
Unit
175
ps
225
8
ns
10
ns
MHz
100
ps
300
100
ps
150
ps
1
ms
Max
500
200
125
83.33
62.5
41.67
200
75
1.0
200
125
83.33
62.5
41.67
52
56
1.0
200
125
Unit
MHz
MHz
%
ns
MHz
%
ns
ps
ps
Page 5 of 9
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