CY23S08_09 Datasheet, PDF (5/11 Pages) Cypress Semiconductor – 3.3V Zero Delay Buffer

CY23S08
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices (continued)
Parameter^[8]
Name
Test Conditions
t3
Rise Time^[7] (–1, –2, –3, –4) ^{Measured between 0.8V and 2.0V, 30 pF}
load
t3
Rise Time^[7] (–1, –2, –3, –4) ^{Measured between 0.8V and 2.0V, 15 pF}
load
t3
Rise Time^[7] (–1H, -2H) ^{Measured between 0.8V and 2.0V, 30 pF}
load
t₄
Fall Time^[7] (–1, –2, –3, –4) ^{Measured between 0.8V and 2.0V, 30 pF}
load
t₄
Fall Time^[7] (–1, –2, –3, –4) ^{Measured between 0.8V and 2.0V, 15 pF}
load
t₄
Fall Time^[7] (–1H, 2H)
Measured between 0.8V and 2.0V, 30 pF
load
t₅
Output to Output Skew on All outputs equally loaded
same Bank (–1)^[7]
Output to Output Skew on All outputs equally loaded
same Bank
(–1H,–2,–2H,–3)^[7]
Output to Output Skew on All outputs equally loaded
same Bank (–4)^[7]
Output to Output Skew
(–1H, -2H)
All outputs equally loaded
Output Bank A to Output All outputs equally loaded
Bank B Skew (–1,–2, –3)
Output Bank A to Output All outputs equally loaded
Bank B Skew (–4)
Output Bank A to Output All outputs equally loaded
Bank B Skew (–1H)
t₆
Delay, REF Rising Edge to
FBK Rising Edge^[7]
Measured at V_DD/2
t₇
Device to Device Skew^{[7] Measured at V}DD^{/2 on the FBK pins of}
devices
t₈
Output Slew Rate^[7]
Measured between 0.8V and 2.0V on –1H,
–2H device using Test Circuit #2
t_J
Cycle to Cycle Jitter^[7]
Measured at 66.67 MHz, loaded outputs, 15,
(–1, –1H)
30 pF loads: 133 MHz, 15 pF load
Cycle to Cycle Jitter^[7]
(–2)
Measured at 66.67 MHz, loaded outputs,
15 pF load
Cycle to Cycle Jitter^[7]
(–2)
Measured at 66.67 MHz, loaded outputs,
30 pF load
t_J
Cycle to Cycle Jitter^[7]
Measured at 66.67 MHz, loaded outputs
(–3,–4)
15, 30 pF loads
t_LOCK
PLL Lock Time^[7]
Stable power supply, valid clocks presented
on REF and FBK pins
Min
—
—
—
—
—
—
—
—
—
—
—
—
–250
—
1
—
—
—
—
—
Typ.
—
—
—
—
—
—
45
105
70
—
—
—
—
—
—
—
65
85
—
—
—
Max
2.20
1.50
1.50
2.20
1.50
1.25
200
150
100
200
300
215
250
+275
700
125
300
400
200
1.0
Unit
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
V/ns
ps
ps
ps
ps
ms
Document #: 38-07265 Rev. *I
Page 5 of 11
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