CY23S08_09 Datasheet, PDF (3/11 Pages) Cypress Semiconductor – 3.3V Zero Delay Buffer

CY23S08
Table 2. Select Input Decoding
S2
S1
CLOCK A1–A4
0
0
Three-State
0
1
Driven
1
0
Driven
1
1
Driven
CLOCK B1–B4
Three-State
Three-State
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
Y
N
Y
N
Table 3. Available CY23S08 Configurations
Device
CY23S08–1
CY23S08–1H
CY23S08–2
CY23S08–2H
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank A
Bank A Frequency
Reference
Reference
Reference
Reference
CY23S08–2
CY23S08–2H
Bank B
Bank B
2 X Reference
2 X Reference
CY23S08–3
CY23S08–3
CY23S08–4
Bank A
Bank B
Bank A or Bank B
2 X Reference
4 X Reference
2 X Reference
Bank B Frequency
Reference
Reference
Reference/2
Reference/2
Reference
Reference
Reference or Reference^[4]
2 X Reference
2 X Reference
Spread Aware
Many systems designed now use the Spread Spectrum Frequency Timing Generation (SSFTG) technology. Cypress is one of the
pioneers of SSFTG development, and designed this product so as not to filter off the Spread Spectrum feature of the Reference input,
assuming it exists. When a zero delay buffer does not pass through the SS feature, the result is a significant amount of tracking skew
which may cause problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology, please see Cypress’s application note EMI Suppression Techniques with
Spread Spectrum Frequency Timing Generator (SSFTG) ICs.
Note
4. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08–2.
Document #: 38-07265 Rev. *I
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