CY2220 Datasheet, PDF (5/11 Pages) Cypress Semiconductor – 133-MHz Spread Spectrum Clock Synthesizer/Driver With Differential CPU Outputs

CY2220
- _{Switching Characteristics[4] Over the Operating Range}
Parameter
t₁
t₂
t₂
t₂
t₃
t₃
t₃
t₄
t₅
t₆
t₇
t₈
Output
All
CPU
USB, REF
PCI, 3V66,
MemRef
CPU
USB, REF
PCI, 3V66,
MemRef
CPU
3V66
PCI
3V66,PCI
CPU
t₉
Mref
t₉
3V66
t₉
USB
t₉
PCI
t₉
REF
CPU, PCI
CPU
CPU
Description
Output Duty Cycle^[5]
Rise Time
Rising Edge Rate
Rising Edge Rate
Fall Time
Falling Edge Rate
Falling Edge Rate
CPU-CPU Skew
3V66-3V66 Skew
PCI-PCI Skew
3V66-PCI Clock Skew
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Settle Time
Rise/Fall Matching
Overshoot
Test Conditions
t_1A/(t_1B)
Measured at 20% to 80% of V_OH
Between 0.4V and 2.4V
Between 0.4V and 2.4V
Measured at 80% to 20% of V_OH
Between 2.4V and 0.4V
Between 2.4V and 0.4V
Measured at Crossover
Measured at 1.5V
Measured at 1.5V
3V66 leads. Measured at 1.5V
Measured at Crossover t₈ = t_8A – t_8B
With all outputs running
Measured at 1.5V t₉ = t_9A – t_9B
Measured at 1.5V t₉ = t_9A – t_9B
Measured at 1.5V t₉ = t_9A – t_9B
Measured at 1.5V t₉ = t_9A – t_9B
Measured at 1.5V t₉ = t_9A – t_9B
CPU and PCI clock stabilization from
power-up
Measured with test loads^{[6, 7]}
Measured with test loads^[7]
Min.
45
175
0.5
1.0
175
0.5
1.0
1.5
CPU
Undershoot
Measured with test loads^[7]
–0.2
V_oh
V_ol
V_crossover
CPU
CPU
CPU
High-level Output Voltage
Low-level Output Voltage
Crossover Voltage
Measured with test loads^[7]
Measured with test loads^[7]
Measured with test loads^[7]
0.65
0.0
45%
of
V_OH
Notes:
4. All parameters specified with loaded outputs. Parameters not tested in production, but are guaranteed by design characterization.
5. Duty cycle is measured at 1.5V with V_DD at 3.3V on all output except CPU. Duty Cycle on CPU is measured at V_Crossover.
6. Determined as a fraction of 2*(t_RP – t_RN)/(t_RP + t_RN)Where t_RP is a rising edge and t_RN is an intersecting falling edge.
7. The test load is specified in test circuit.
Max.
55
700
2.0
4.0
700
2.0
4.0
150
250
500
3.5
200
250
300
350
500
1000
3
20%
V_OH +
0.2
0.74
0.05
55%
of
V_OH
Unit
%
ps
V/ns
V/ns
ps
V/ns
V/ns
ps
ps
ps
ns
ps
ps
ps
ps
ps
ps
ms
V
V
V
V
V
Document #: 38-07206 Rev. *A
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