CY15B256Q Datasheet, PDF (5/22 Pages) Cypress Semiconductor – 256-Kbit (32K × 8) Automotive Serial (SPI) F-RAM

CY15B256Q
For a microcontroller that has no dedicated SPI bus, a
general-purpose port may be used. To reduce hardware
resources on the controller, it is possible to connect the two data
pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins.
Figure 3 shows such a configuration, which uses only three pins.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
The 256-Kbit serial F-RAM requires a 2-byte address for any
read or write operation. Because the address is only 15 bits, the
upper bit which is fed in is ignored by the device. Although the
upper bit is ‘don’t care’, Cypress recommends that these bits be
set to 0s to enable seamless transition to higher memory
densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY15B256Q uses the standard opcodes for memory accesses.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin until the
next falling edge of CS, and the SO pin remains tristated.
Status Register
CY15B256Q has an 8-bit Status Register. The bits in the Status
Register are used to configure the device. These bits are
described in Table 3 on page 7.
Figure 2. System Configuration with SPI Port
SCK
MOSI
MISO
SPI
Microcontroller
CS1
HOLD1
WP1
CS2
HOLD2
WP2
SCK SI SO
CY15B256Q
CS HOLD WP
SCK SI SO
CY15B256Q
CS HOLD WP
Figure 3. System Configuration without SPI Port
P1.0
P1.1
Microcontroller
SCK SI SO
CY15B256Q
CS HOLD WP
P1.2
SPI Modes
CY15B256Q may be driven by a microcontroller with its SPI
peripheral running in either of the following two modes:
■ SPI Mode 0 (CPOL = 0, CPHA = 0)
■ SPI Mode 3 (CPOL = 1, CPHA = 1)
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles is considered. The output data
is available on the falling edge of SCK.The two SPI modes are
shown in Figure 4 on page 6 and Figure 5 on page 6. The status
of the clock when the bus master is not transferring data is:
■ SCK remains at 0 for Mode 0
■ SCK remains at 1 for Mode 3
Document Number: 001-90867 Rev. *E
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